pld考试程序总结6.doc

1 三态门 library ieee; use ieee.std_logic_1164.all; entity three is port( a,en:in std_logic; y:out std_logic); end three; architecture bhv of three is begin process(a,en) begin if en=1 then y=a ; else y=Z; end if; end process; end bhv; 2. 用条件信号赋值语句设计8位比较器 library ieee; use ieee.std_logic_1164.all; entity comp8 is port(a,b: in std_logic_vector(0 to 7); gt,eq,lt: out std_logic); end comp8; architecture a of comp8 is signal c:std_logic_vector(0 to 2); begin cb else 010 when a=b else 001 when ab else 000; gt=c(0);eq=c(1);lt=c(2); end a ;3 检测8位二进制数中1的个数并用数码管显示检测结果 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count_dec is port( a: in std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0); end count_dec; architecture str of count_dec is signal temp:std_logic_vector(0 to 3); begin P1: process(a) variable cnt:std_logic_vector(0 to 3); begin cnt:=0000; for i in 0 to 7 loop if a(i)=1 then cnt:=cnt+1; end if; end loop; templedledledledledledledledledled=0000000; end case; end process; end str;4. N输入与门设计 library ieee; use ieee.std_logic_1164.all; entity andn is generic(n:integer:=8); port(a:in std_logic_vector( 0 to n-1); y:out std_logic); end andn; architecture hbv of andn is begin process(a) variable tmp:std_logic; begin tmp:=1; for i in 0 to alength-1 loop if a(i)=0then tmp:=0; end if; end loop; y2) port map(d(0 to 1),y1); u2:andn generic map(n=3) port map(d(2 to 4),y2); end hbv; 6. 七人表决器library ieee;use ieee.std_logic_1164.all;entity vote7 isport(a:in std_logic_vector( 0 to 6);lg,lr:out std_logic);end;architecture bhv of vote7 issignal pass:integer;beginprocess(a)variable tmp1:integer;begintmp1:=0;for i in 0 to 6 loopif a(i)=1 then tmp1:=tmp1+1; else tmp1:=tmp1+0;end if;end loop;pass=tmp1;end process;lg=4 else 0;lr=1when pass4 else 0;end bhv;7. 串行数据检测器的设计library ieee;use ieee.std_logic_1164.all;entity scheck isport(,clk,clr:in std_logic; y:out std_logic);end scheck;architecture b of scheck issignal s:integer range 0 to 8;signal d:std_logic_vector(7 downto 0);begind=10001110;p1:process(clr,clk) begin if clr=1then sif din=d(7)then s=1;else sif din=d(6)then s=2;else sif din=d(5)then s=3;else sif din=d(4)then s=4;else sif din=d(3)then s=5;else sif din=d(2)then s=6;else sif din=d(1)then s=7;else sif din=d(0)then s=8;else ss=0; end case; end if;end process;p2:process(s) begin if s=8 then y=1; else y=0; end if;end process;end b;8. 4选1数据选择器的设计（设计方法不唯一）library ieee;use ieee.std_logic_1164.all;entity mux41 isport(a,b,en:in std_logic; d:in std_logic_vector(0 to 3); y:out std_logic);End mux41;architecture bhv of mux41 issignal sel:std_logic_vector(0 to 1);beginsel=a&b;with sel selecty=d(0) when 00, d(1) when 01, d(2) when 10, d(3) when 11, Z when others;end bhv;