pld考试程序总结6.doc

1 三态门
• library ieee;
• use ieee.std_logic_1164.all;
• entity three is
• port( a,en:in std_logic;
• y:out std_logic);
• end three;
• architecture bhv of three is
• begin
• process(a,en)
• begin
• if en='1' then y<=a ;
• else y<='Z';
• end if;
• end process;
• end bhv;

2. 用条件信号赋值语句设计8位比较器
• library ieee;
• use ieee.std_logic_1164.all;
• entity comp8 is
• port(a,b: in std_logic_vector(0 to 7);
• gt,eq,lt: out std_logic);
• end comp8;
• architecture a of comp8 is
• signal c:std_logic_vector(0 to 2);
• begin
• c<="100" when a>b else
• "010" when a=b else
• "001" when aic_1164.all;
• use ieee.std_logic_unsigned.all;
• entity count_dec is
• port( a: in std_logic_vector(7 downto 0);
• led:out std_logic_vector(6 downto 0));
• end count_dec;
• architecture str of count_dec is
• signal temp:std_logic_vector(0 to 3);
• begin
• P1: process(a)
• variable cnt:std_logic_vector(0 to 3);
• begin
• cnt:="0000";
• for i in 0 to 7 loop
• if a(i)='1' then
• cnt:=cnt+1;
• end if;
• end loop;
• temp<=cnt;
• end process;
• p2: process(temp)
• begin
• case temp is
• when"0000"=>led<="0111111";
• when"0001"=>led<="0000110";
• when"0010"=>led<="1011011";
• when"0011"=>led<="1001111";
• when"0100"=>led<="1100110";
• when"0101"=>led<="1101101";
• when"0110"=>led<="1111101";
• when"0111"=>led<="0000111";
• when"1000"=>led<="1111111";
• when others=>led<="0000000";
• end case;
• end process;
end str;

4. N输入与门设计
• library ieee;
• use ieee.std_logic_1164.all;
• entity andn is
• generic(n:integer:=8);
• port(a:in std_logic_vector( 0 to n-1);

• y:out std_logic);
• end andn;
• architecture hbv of andn is
• begin
• process(a)
• variable tmp:std_logic;
• begin
• tmp:='1';
• for i in 0 to a'length-1 loop
• if a(i)='0'then tmp:='0';
• end if;
• end loop;
• y<=tmp;
• end process;end hbv;

5．调用N输入与门实现2输入和3输入与门设计
• library ieee;
• use ieee.std_logic_1164.all;
• entity andcom is
• port(d:in std_logic_vector(0 to 4);
• y1,y2:out std_logic);
• end andcom;
• architecture hbv of andcom is
• component andn
• generic(n:integer:=8);
• port(a:in std_logic_vector( 0 to n-1);
• y:out std_logic);
• end component;
• begin
• u1:andn generic map(n=>2) port map(d(0 to 1),y1);
• u2:andn generic map(n=>3) port map(d(2 to 4),y2);
• end hbv;

6. 七人表决器
library ieee;
use ieee.std_logic_1164.all;
entity vote7 is
port(a:in std_logic_vector( 0 to 6)
lg,lr:out std_logic);
end;
architecture bhv of vote7 is
signal pass:integer;
begin
process(a)
variable tmp1:integer;
begin
tmp1:=0;
for i in 0 to 6 loop
if a(i)='1' then tmp1:=tmp1+1;
else tmp1:=tmp1+0;
end if;
end loop;
pass<=tmp1;
end process;
lg<='1'when pass>=4 else
'0';
lr<='1'when pass<4 else
'0';
end bhv;

7. 串行数据检测器的设计
library ieee;
use ieee.std_logic_1164.all;
entity scheck is
port(,clk,clr:in std_logic;
y:out std_logic);
end scheck;
architecture b of scheck is
signal s:integer range 0 to 8;
signal d:stdlogic_vector(7 downto 0);
begin
d<="10001110";
p1:process(clr,clk)
begin
if clr='1'then s<=0;
elsif clk'event and clk='1'then
case s is
when 0=>if din=d(7)then s<=1;else s<=0;end if;
when 1=>if din=d(6)then s<=2;else s<=1;end if;
when 2=>if din=d(5)then s<=3;else s<=1;end if;
when 3=>if din=d(4)then s<=4;else s<=1;end if;
when 4=>if din=d(3)then s<=5;else s<=0;end if;
when 5=>if din=d(2)then s<=6;else s<=2;end if;
when 6=>if din=d(1)then s<=7;else s<=2;end if;
when 7=>if din=d(0)then s<=8;else s<=1;end if;
when others=>s<=0;
end case;
end if;
end process;
p2:process(s)
begin
if s=8 then y<=’1’;
else y<=’0’;
end if;
end process;
end b;

8. 4选1数据选择器的设计（设计方法不唯一）
library ieee;
use ieee.std_logic_1164.all;
entity mux41 is
port(a,b,en:in std_logic;
d:in std_logic_vector(0 to 3);
y:out std_logic);
End mux41;
architecture bhv of mux41 is
signal sel:std_logic_vector(0 to 1);
begin
sel<=a&b;
with sel select
y<=d(0) when "00",
d(1) when "01",
d(2) when "10",
d(3) when "11",
'Z' when others;
end bhv;