静态时序分析基本原理和时序分析模型.ppt

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,*,Quartus,II Software Design Series:Timing Analysis,-,Timing analysis basics,2,Objectives,Display a complete understanding of timing analysis,3,How does timing verification work?,Every device path in design must be analyzed with respect to timing specifications/requirements,Catch timing-related errors faster and easier than gate-level simulation&board testing,Designer must enter timing requirements&exceptions,Used to guide fitter during placement&routing,Used to compare against actual results,IN,CLK,OUT,D,Q,CLR,PRE,D,Q,CLR,PRE,combinational delays,CLR,4,Timing Analysis Basics,Launch vs.latch edges,Setup&hold times,Data&clock arrival time,Data required time,Setup&hold slack analysis,I/O analysis,Recovery&removal,Timing models,5,Path&Analysis Types,Three types of Paths:,Clock Paths,Data Path,Asynchronous Paths*,Clock Paths,Async Path,Data Path,Async Path,D,Q,CLR,PRE,D,Q,CLR,PRE,Two types of Analysis:,Synchronous clock&data paths,Asynchronous*clock&async paths,*,Asynchronous refers to signals feeding the asynchronous control ports of the registers,6,Launch&Latch Edges,CLK,Launch Edge,Latch Edge,Data Valid,DATA,Launch Edge:the edge which“launches”the data from source register,Latch Edge:the edge which“latches”the data at destination register(with respect to the launch edge,selected by timing analyzer;typically 1 cycle),7,Setup&Hold,Setup:The minimum time data signal must be stable,BEFORE clock edge,Hold:The minimum time data signal must be stable,AFTER clock edge,D,Q,CLR,PRE,CLK,T,h,Valid,DATA,T,su,CLK,DATA,Together,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.,8,Data Arrival Time,Data Arrival Time=launch edge+T,clk1,+T,co,+T,data,CLK,REG1.CLK,T,clk1,Data Valid,REG2.D,T,data,Launch,Edge,Data Valid,REG1.Q,T,co,The time for data to arrive at destination registers D input,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk1,T,CO,T,data,9,Clock Arrival Time,Clock Arrival Time=latch edge+T,clk2,CLK,REG2.CLK,T,clk2,Latch,Edge,The time for clock to arrive at destination registers clock input,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk2,10,Data Required Time-Setup,Data Required Time=Clock Arrival Time,-,T,su,-Setup Uncertainty,CLK,REG2.CLK,T,clk2,Latch,Edge,The minimum time required for the data to get latched into the destination register,T,su,Data Valid,REG2.D,Data must be valid here,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk2,T,su,11,Data Required Time-Hold,Data Required Time=Clock Arrival Time+T,h,+Hold Uncertainty,CLK,REG2.CLK,T,clk2,Latch,Edge,The minimum time required for the data to get latched into the destination register,T,h,Data must,remain valid,to here,Data Valid,REG2.D,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk2,T,h,12,T,clk2,Setup Slack,REG2.CLK,The margin by which the setup timing requirement is met.It ensures launched data arrives in time to meet the latching requirement.,T,su,CLK,REG1.CLK,T,clk1,Data Valid,REG2.D,T,data,Data Valid,REG1.Q,T,co,Setup,Slack,Launch,Edge,Latch,Edge,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk1,T,CO,T,data,T,clk2,T,su,13,Setup Slack(contd),Positive slack,Timing requirement met,Negative slack,Timing requirement not met,Setup Slack=Data Required Time,Data Arrival Time,14,Hold Slack,REG2.CLK,T,clk2,The margin by which the hold timing requirement is met.It ensures latch data is not corrupted by data from another launch edge.,T,h,CLK,REG1.CLK,T,clk1,Data Valid,REG2.D,T,data,Data Valid,REG1.Q,T,co,Hold,Slack,Latch,Edge,Next Launch,Edge,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk1,T,CO,T,data,T,clk2,T,h,15,Hold Slack(contd),Positive slack,Timing requirement met,Negative slack,Timing requirement not met,Hold Slack=Data Arrival Time,Data Required Time,16,FPGA/CPLD or ASSP,ASSP or FPGA/CPLD,I/O Analysis,Analyzing I/O performance in a synchronous design uses the same slack equations,Must include external device&PCB timing parameters,reg1,PRE,D Q,CLR,reg2,PRE,D Q,CLR,C,L,*,T,data,T,clk1,T,clk2,T,CO,T,su,/T,h,OSC,Data Arrival Path,Data Arrival Path,Data Required Path,*,Represents delay due to capacitive loading,17,Recovery&Removal,Recovery:The minimum time an asynchronous signal must,be stable BEFORE clock edge,Removal:The minimum time an asynchronous signal must,be stable AFTER clock edge,D,Q,CLR,SET,CLK,T,rem,Valid,ASYNC,T,rec,CLK,ASYNC,18,Asynchronous=Synchronous?,Asynchronous control signal source is assumed synchronous,Slack equations still apply,data arrival path=asynchronous control path,T,su,T,rec,;T,h,T,rem,External device&board timing parameters may be needed(Ex.1),ASSP,reg1,PRE,D Q,CLR,FPGA/CPLD,reg2,PRE,D Q,CLR,OSC,FPGA/CPLD,reg1,PRE,D Q,CLR,reg2,PRE,D Q,CLR,Example 1,Example 2,Data arrival path,Data arrival path,Data required path,Data required path,19,Why Are These Calculations Important?,Calculations are important when timing violations occur,Need to be able to understand cause of violation,Example causes,Data path too long,Requirement too short(incorrect analysis),Large clock skew signifying a gated clock,etc.,TimeQuest timing analyzer uses them,Equations to calculate slack,Terminology(launch and latch edges,Data Arrival Path,Data Required Path,etc.)in timing reports,20,Timing Models in Detail,Quartus II software models device timing at two PVT conditions by default,Slow Corner,Model,Indicates slowest possible performance for any single path,Timing for slowest device at maximum operating temperature and VCC,MIN,Fast Corner,Model,Indicates fastest possible performance for any single path,Timing for fastest device at minimum operating temperature and VCC,MAX,Why two corner timing models?,Ensure,setup,timing is met in,slow,model,Ensure,hold,timing is met in,fast,model,Essential for source synchronous interfaces,Third model(slow,min.temp.)available only for 65 nm and smaller technology devices(temperature inversion phenomenon),21,Generating Fast/Slow Netlist,Specify one of the default timing models to be used when creating your netlist,Default is the slow timing netlist,To specify fast timing netlist,Use,-fast_model,option with,create_timing_netlist,command,Choose,Fast corner,in GUI when,executing,Create Timing Netlist,from,Netlist,menu,CANNOT select fast corner,from Tasks Pane,22,Specifying Operating Conditions,Perform timing analysis for different delay models without recreating the existing timing netlist,Takes precedence over already generated netlist,Required for selecting slow,min.temp.model and other models(industrial,military,etc.)depending on device,Use,get_available_operating_conditions,to see available conditions for target device,Reference Documents,Quartus II Handbook,Volume 3,Chapter 7 The Quartus II TimeQuest Timing Analyzer,Start Tutorial,Documents,SDC and TimeQuest API Reference Manual,481:Applying Multicycle Exceptions in the TimeQuest Timing Analyzer,433:Constraining and Analyzing Source-Synchronous Interfaces,Training,With Alteras instructor-led training courses,you can:,Listen to a lecture from an Altera technical training engineer(instructor),Complete hands-on exercises with guidance from an Altera instructor,Ask questions&receive real-time answers from an Altera instructor,Each instructor-led class is one or two days in length(8 working hours per day).,Online Training,With Alteras online training courses,you can:,Take a course at any time that is convenient for you,Take a course from the comfort of your home or office(no need to travel as with instructor-led courses),Each online course will take approximate one to three hours to complete.,training class schedule&register for a class,Learn More Through Technical Training,26,Altera Technical Support,Reference Quartus II software on-line help,Quartus II Handbook,Consult Altera applications(factory applications engineers),MySupport:,(800)800-EPLD(7:00 a.m.-5:00 p.m.PST),Field applications engineers:contact your local Altera sales office,Receive literature by mail:(888)3-ALTERA,FTP:,World-wide web:,Use solutions to search for answers to technical problems,View design examples,