EDA技术与Verilog设计第六章课后习题部分答案PPT课件.ppt

6-116-11 试编写求补码的Verilog程序，输入是带符号的8位二进制数module wytest(data_in,data_out);/习题6-11 input7:0 data_in;output7:0 data_out;reg7:0 data_out;always(data_in)begin if(data_in7)/正数负数判断，从最高是否为1来判断 data_out=(data_in)+1)|8h80;else data_out=data_in;end endmodule16-11仿真波形8A-原码表示的十进制数-10 0A-十进制数10B6-原码表示的十进制数-54 36-十进制数5380-原码表示的十进制数12826-12 6-12 编写两个四位二进制数相减的verilog程序v module wytest(opr1,opr2,out_data);/完成Opr1-opr2的运算v input3:0 opr1,opr2;v output4:0 out_data;v v reg3:0 out;v reg cout;v function3:0 abs;v input3:0 data;v case(data3)v 1b0:abs=data;v 1b1:abs=(data)+1;/对负数求绝对值，按位取反再加1v endcasev endfunction 36-12valways(opr1 or opr2)v case(opr13,opr23)v 2b00:cout,out=opr1-opr2;/两个正数相减v 2b01:cout,out=opr1+abs(opr2);/正数减负数，化为加v 法运算v 2b10:cout,out=-(abs(opr1)+opr2);/负数减正数，化为加v 法再取反 v 2b11:cout,out=abs(opr2)-abs(opr1);/负数相减，化为绝v 对值相减（顺序调换）v endcasev vassign out_data=cout,out;v vendmodule46-126-12 仿真波形56-13 6-13 有一个比较电路，当输入的一位BCD码 大于4时，输出1，否则输出0。module wytest(bcd_in,out);input3:0 bcd_in;output out;assign out=(bcd_in4)?1:0;endmodule66-13仿真波形76-13vmodule wytest(bcd_in,out);/习题6-13v input3:0 bcd_in;v output out;v /assign out=(bcd_in4)?1:0;v v reg out;v always(bcd_in)v if(bcd_in-40)v out=1;v elsev out=0;vendmodule86-1396-14试编写一个实现3输入与非门的verilog程序；vmodule wytest(a,o);vinput2:0 a;voutput o;vnand nand3(o,a0,a1,a2);vendmodule106-14116-156-15 设计74138译码器电路 126-15vmodule wytest(s1,s2,in,out);vinput s1;vinput1:0 s2;vinput2:0 in;voutput7:0 out;vreg8:0 out;valways(s1 or s2 or in)vbeginv if(s1=0)v out=8hff;v else if(!s20)|(!s21)v out=8hff;velsev case(in)v 3d0:out=8b11111110;v 3d1:out=8b11111101;v 3d2:out=8b11111011;v 3d3:out=8b11110111;v 3d4:out=8b11101111;v 3d5:out=8b11011111;v 3d6:out=8b10111111;v 3d7:out=8b01111111;v endcasevendvendmodule 136-15146-16CO=Q3 Q2 Q1 Q0 CTT注意：异步清零、同步置位6-16 设计一个74161的电路。156-16vmodule wytest(reset,load,ctt,ctp,clk,data_in,out,co);/习题6-16vinput reset,load,ctt,ctp,clk;vinput3:0 data_in;voutput3:0 out;voutput co;vreg3:0 out;vreg co;valways(posedge clk or negedge reset)v v if(!reset)v beginv out=4b0;v co=1b0;v endv else if(!load)v out=data_in;v else if(!ctt)v out=out;v else if(!ctp)v out=out;v elsev beginv out=out+1;v if(out=14)v co=1;v elsev co=0;v endvendmodule 166-1617四级流水线实现的32位加法器module wytest(clk,a,b,sum,cout);input31:0 a,b;input clk;output31:0 sum;output cout;/最后输出的结果reg31:0 sum;reg cout;/第一级流水线的输出reg7:0 fist_sum;reg first_cout;/第一级流水线要缓存的数据/未用的数据缓存 reg7:0 first_a_31_24,first_a_23_16,first_a_15_8;reg7:0 first_b_31_24,first_b_23_16,first_b_15_8;18四级流水线实现的32位加法器v/第二级流水线的输出vreg7:0 second_sum;vreg second_cout;v/第二级流水线要缓存的数据v/未用的数据缓存 vreg7:0 second_a_31_24,second_a_23_16;vreg7:0 second_b_31_24,second_b_23_16;v/第一级流水线计算结果缓存vreg7:0 first_sum_1;/第一级流水线计算结果第一次缓存v/第三级流水线输出vreg7:0 third_sum;vreg third_cout;v/第三级流水线要缓存的数据v/未用的数据缓存 vreg7:0 third_a_31_24;vreg7:0 third_b_31_24;v/第一级、第二级流水线计算结果缓存vreg7:0 first_sum_2;/第一级流水线计算结果第二次缓存；vreg7:0 second_sum_1;/第二级流水线计算结果第一次缓存；19四级流水线实现的32位加法器/第一级流水线always(posedge clk)begin first_cout,fist_sum=a7:0+b7:0+cout;first_a_31_24=a31:24;first_b_31_24=b31:24;first_a_23_16=a23:16;first_b_23_16=b23:16;first_a_15_8=a15:8;first_b_15_8=b15:8;end/第二级流水线always(posedge clk)begin second_cout,second_sum=first_a_15_8+first_b_15_8+first_cout;second_a_31_24=first_a_31_24;second_b_31_24=first_b_31_24;second_a_23_16=first_a_23_16;second_b_23_16=first_b_23_16;first_sum_1=fist_sum;end20四级流水线实现的32位加法器/第三级流水线always(posedge clk)beginthird_cout,third_sum=second_a_23_16+second_b_23_16+second_cout;third_a_31_24=second_a_31_24;third_b_31_24=second_b_31_24;first_sum_2=first_sum_1;second_sum_1=second_sum;end/第四级流水线always(posedge clk)begin cout,sum31:24=third_a_31_24+third_b_31_24+third_cout;sum23:0=third_sum,second_sum_1,first_sum_2;endendmodule21四级流水线实现的32位加法器228x8乘法器实现module wytest(out,a,b,clk);input7:0 a,b;input clk;output15:0 out;reg15:0 out;reg3:0 firsta,firstb;reg3:0 seconda,secondb;wire7:0 outa,outb,outc,outd;always(posedge clk)begin firsta3:0=a7:4;seconda3:0=a3:0;firstb3:0=b7:4;secondb3:0=b3:0;endmul4x4 m1(outa,firsta,firstb,clk),m2(outb,seconda,firstb,clk),m3(outc,firsta,secondb,clk),m4(outd,seconda,secondb,clk);always(posedge clk)out=(outa8)+(outb4)+(outc 4)+outd;endmodule238x8乘法器实现用另一种方法实现：将8位数字分成4段，每段两位，那么操作数可表示如下：A=A1X26+A2X24+A3X22+A4 B=B1X26+B2X24+B3X22+B4 AXB=(A1X26+A2X24+A3X22+A4)X(B1X26+B2X24+B3X22+B4)上式展开后，要做16次2X2的乘法，调用16次lookup函数 然后再做移位相加的处理。247-5 编写4位并-串转换电路module wytest(clk,rst,in,out);input clk,rst;input3:0 in;output out;reg out;reg1:0 i;always(posedge clk)begin if(rst)begin i=2d0;out=1d0;end else if(i=3)begin out=ini;i=i+1;end end25模为9的占空比50%的奇数分频vmodule wytest(RESET,CLK,COUT);vinput CLK,RESET;output COUT;vreg3:03:0 m,n;vwire COUT;vreg COUT1,COUT2;vassign COUT=COUT1|COUT2;valways(posedge CLK)vbeginv if(!RESET)v begin v COUT1=0;/输出信号初出信号初态为0v m=0;/计数初数初值为0v endelse if(RESET)begin if(m=8)/n-1 begin m=0;end else m=m+1;if(m=3)/N/2-1.5 COUT1=COUT1;else if(m=7)/N-2 COUT1=COUT1;endend26always(negedge CLK)begin if(!RESET)begin COUT2=0;n=0;endelse if(RESET)begin if(n=8)begin n=0;end else n=n+1;if(n=3)COUT2=COUT2;else if(n=7)COUT2=COUT2;endendEndmodule模为9的占空比50%的奇数分频27模为9.3的小数分频分分频方法方法：9分分频7次，次，10分分频3次次vmodule fdiv8_1(clk_in,rst,clk_out);vinput clk_in,rst;voutput clk_out;vreg clk_out;vreg3:0 cnt1;/cnt1计8分分频的次数的次数vreg3:0 cnt2;/cnt2为两个分两个分频器的器的计数数值valways(posedge clk_in or posedge rst)vbeginv if(rst)v begin v cnt1=0;cnt2=0;clk_out=0;v endv else if(cnt17)/9分分频7次次v begin v if(cnt28)/9分分频的前的前8个脉冲的个脉冲的处理理v begin v cnt2=cnt2+1;v clk_out=0;v endv else /处理最后一个理最后一个输入脉冲入脉冲v beginv cnt2=0;v clk_out=1;v cnt1=cnt1+1;v end v end28模为9.3的小数分频 else if(cnt110cnt110)begin if(cnt29cnt29)/10分频的前9个脉冲处理 begin cnt2=cnt2+1;clk_out=0;end else begin cnt2=0;clk_out=1;if if（cnt1=9cnt1=9）cnt1=0;cnt1=0;else cnt1=cnt1+1;else cnt1=cnt1+1;end endendendmodule29习题10-3 “1001”二进制序列检测器S0S1S2S31/00/00/00/01/11/01/00/0RESET30vmodule wytest(reset,clk,in,out);vinput reset,clk,in;voutput out;vreg out;vreg1:0 state,next_state;vparameter s0=2d0,s1=2d1,s2=2d2,s3=2d3;valways(posedge clk)vbeginv if(!reset)v state=s0;v elsev state=next_state;vendvalways(state or in)vcase(state)vs0:if(in=1)next_state=s1;v else next_state=s0;vs1:if(in=0)next_state=s2;v else next_state=s1;vs2:if(in=0)next_state=s3;v else next_state=s1;vs3:if(in=1)next_state=s1;v else next_state=s0;vdefault:next_state=s0;vendcasealways(state or in)case(state)s0:if(in=1)out=0;else out=0;s1:if(in=0)out=0;else out=0;s2:if(in=0)out=0;else out=0;s3:if(in=1)out=1;else out=0;default:out=0;endcaseendmodule31