嵌入式开发-CD00220591.pdf

This is information on a product in full production.March 2014DocID15275 Rev 131/84STM8L101xx8-bit ultralow power microcontroller with up to 8 Kbytes Flash,multifunction timers,comparators,USART,SPI,I2CDatasheet-production dataFeaturesMain microcontroller featuresSupply voltage range 1.65 V to 3.6 VLow power consumption(Halt:0.3 A,Active-halt:0.8 A,Dynamic Run:150 A/MHz)STM8 Core with up to 16 CISC MIPS throughputTemp.range:-40 to 85 C and 125 CMemoriesUp to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROMError correction code(ECC)Flexible write and read protection modesIn-application and in-circuit programmingData EEPROM capability1.5 Kbytes of static RAMClock managementInternal 16 MHz RC with fast wakeup time(typ.4 s)Internal low consumption 38 kHz RC driving both the IWDG and the AWUReset and supply managementUltralow power POR/PDRThree low power modes:Wait,Active-halt,HaltInterrupt managementNested interrupt controller with software priority controlUp to 29 external interrupt sourcesI/OsUp to 30 I/Os,all mappable on external interrupt vectorsI/Os with prog.input pull-ups,high sink/source capability and one LED driver infrared outputPeripheralsTwo 16-bit general purpose timers(TIM2 and TIM3)with up and down counter and 2 channels(used as IC,OC,PWM)One 8-bit timer(TIM4)with 7-bit prescalerInfrared remote control(IR)Independent watchdogAuto-wakeup unitBeeper timer with 1,2 or 4 kHz frequenciesSPI synchronous serial interface Fast I2C Multimaster/slave 400 kHzUSART with fractional baud rate generator2 comparators with 4 inputs eachDevelopment supportHardware single wire interface module(SWIM)for fast on-chip programming and non intrusive debuggingIn-circuit emulation(ICE)96-bit unique IDTable 1.Device summaryReferencePart numbersSTM8L101xxSTM8L101F1,STM8L101F2,STM8L101F3,STM8L101G2,STM8L101G3 STM8L101K3UFQFPN28 UFQFPN32 LQFP32 TSSOP20 UFQFPNDocID15275 Rev 133/84STM8L101xxContents4Contents1Introduction.82Description.83Product overview .103.1Central processing unit STM8 .113.2Development tools .113.3Single wire data interface(SWIM)and debug module.113.4Interrupt controller .113.5Memory .123.6Low power modes .123.7Voltage regulators .123.8Clock control.123.9Independent watchdog.123.10Auto-wakeup counter.133.11General purpose and basic timers.133.12Beeper .133.13Infrared(IR)interface.133.14Comparators.133.15USART.143.16SPI.143.17IC .144Pin description .155Memory and register map.236Interrupt vector mapping .327Option bytes .348Unique ID .36ContentsSTM8L101xx4/84DocID15275 Rev 139Electrical parameters .379.1Parameter conditions.379.1.1Minimum and maximum values.379.1.2Typical values .379.1.3Typical curves .379.1.4Loading capacitor .379.1.5Pin input voltage .389.2Absolute maximum ratings.389.3Operating conditions .409.3.1General operating conditions.409.3.2Power-up/power-down operating conditions .419.3.3Supply current characteristics .419.3.4Clock and timing characteristics .469.3.5Memory characteristics .489.3.6I/O port pin characteristics.499.3.7Communication interfaces.569.3.8Comparator characteristics .609.3.9EMC characteristics.619.4Thermal characteristics .6310Package characteristics.6510.1ECOPACK .6510.2Package mechanical data .6611Device ordering information .7612STM8 development tools .7712.1Emulation and in-circuit debugging tools .7712.2Software tools.7812.2.1STM8 toolset .7812.2.2C and assembly toolchains .7812.3Programming tools.7813Revision history .79DocID15275 Rev 135/84STM8L101xxList of tables5List of tablesTable 1.Device summary.1Table 2.Device features.9Table 3.Legend/abbreviation for table 4 .20Table 4.STM8L101xx pin description .20Table 5.Flash and RAM boundary addresses.24Table 6.I/O Port hardware register map .24Table 7.General hardware register map.25Table 8.CPU/SWIM/debug module/interrupt controller registers.30Table 9.Interrupt mapping.32Table 10.Option bytes.34Table 11.Option byte description.34Table 12.Unique ID registers(96 bits).36Table 13.Voltage characteristics.38Table 14.Current characteristics.39Table 15.Thermal characteristics.39Table 16.General operating conditions.40Table 17.Operating conditions at power-up/power-down .41Table 18.Total current consumption in Run mode .42Table 19.Total current consumption in Wait mode .43Table 20.Total current consumption and timing in Halt and Active-halt mode at VDD=1.65 V to 3.6 V.44Table 21.Peripheral current consumption.45Table 22.HSI oscillator characteristics .46Table 23.LSI oscillator characteristics .47Table 24.RAM and hardware registers.48Table 25.Flash program memory.48Table 26.I/O static characteristics.49Table 27.Output driving current(High sink ports).52Table 28.Output driving current(true open drain ports).52Table 29.Output driving current(PA0 with high sink LED driver capability).52Table 30.NRST pin characteristics .54Table 31.SPI characteristics.56Table 32.I2C characteristics .59Table 33.Comparator characteristics.60Table 34.EMS data.61Table 35.EMI data .62Table 36.ESD absolute maximum ratings.62Table 37.Electrical sensitivities.63Table 38.Thermal characteristics.64Table 39.UFQFPN32-32-lead ultra thin fine pitch quad flat no-lead package(5 x 5),package mechanical data.67Table 40.LQFP32-32-pin low profile quad flat package(7x7),package mechanical data.69Table 41.UFQFPN28-28-lead ultra thin fine pitch quad flat no-lead package(4 x 4),package mechanical data.70Table 42.UFQFPN20-20-lead ulltra thin fine pitch quad flat package(3 x 3 mm)mechanical data 72Table 43.TSSOP20-20-lead thin shrink small package mechanical data.74Table 44.Document revision history .79List of figuresSTM8L101xx6/84DocID15275 Rev 13List of figuresFigure 1.STM8L101xx device block diagram.10Figure 2.Standard 20-pin UFQFPN package pinout.15Figure 3.20-pin UFQFPN package pinout for STM8L101F1U6ATR,STM8L101F2U6ATR and STM8L101F3U6ATR part numbers.16Figure 4.20-pin TSSOP package pinout.17Figure 5.Standard 28-pin UFQFPN package pinout.17Figure 6.28-pin UFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers.18Figure 7.32-pin package pinout .19Figure 8.Memory map.23Figure 9.Pin loading conditions.37Figure 10.Pin input voltage.38Figure 11.IDD(RUN)vs.VDD,fCPU=2 MHz.42Figure 12.IDD(RUN)vs.VDD,fCPU=16 MHz.42Figure 13.IDD(WAIT)vs.VDD,fCPU=2 MHz.43Figure 14.IDD(WAIT)vs.VDD,fCPU=16 MHz.43Figure 15.Typ.IDD(Halt)vs.VDD,fCPU=2 MHz and 16 MHz.44Figure 16.Typical HSI frequency vs.VDD.46Figure 17.Typical HSI accuracy vs.temperature,VDD=3 V.47Figure 18.Typical HSI accuracy vs.temperature,VDD=1.65 V to 3.6 V.47Figure 19.Typical LSI RC frequency vs.VDD.48Figure 20.Typical VIL and VIH vs.VDD(High sink I/Os).50Figure 21.Typical VIL and VIH vs.VDD(true open drain I/Os).50Figure 22.Typical pull-up resistance RPU vs.VDD with VIN=VSS.51Figure 23.Typical pull-up current IPU vs.VDD with VIN=VSS.51Figure 24.Typ.VOL at VDD=3.0 V(High sink ports).53Figure 25.Typ.VOL at VDD=1.8 V(High sink ports).53Figure 26.Typ.VOL at VDD=3.0 V(true open drain ports).53Figure 27.Typ.VOL at VDD=1.8 V(true open drain ports).53Figure 28.Typ.VDD-VOH at VDD=3.0 V(High sink ports).53Figure 29.Typ.VDD-VOH at VDD=1.8 V(High sink ports).53Figure 30.Typical NRST pull-up resistance RPU vs.VDD.54Figure 31.Typical NRST pull-up current Ipu vs.VDD.55Figure 32.Recommended NRST pin configuration.55Figure 33.SPI timing diagram-slave mode and CPHA=0.57Figure 34.SPI timing diagram-slave mode and CPHA=1(1).57Figure 35.SPI timing diagram-master mode(1).58Figure 36.Typical application with I2C bus and timing diagram 1).60Figure 37.UFQFPN32-32-lead ultra thin fine pitch quad flat no-lead package outline(5 x 5).66Figure 38.UFQFPN32 recommended footprint.67Figure 39.LQFP32-32-pin low profile quad flat package outline(7 x 7).68Figure 40.LQFP32 recommended footprint .69Figure 41.UFQFPN28-28-lead ultra thin fine pitch quad flat no-lead package outline(4 x 4).70Figure 42.UFQFPN28 recommended footprint.71Figure 43.UFQFPN20-20-lead ulltra thin fine pitch quad flat package outline (3x3 mm).72Figure 44.UFQFPN20 recommended footprint.73Figure 45.TSSOP20-20-lead thin shrink small package outline .74DocID15275 Rev 137/84STM8L101xxList of figures7Figure 46.TSSOP20 recommended footprint.75Figure 47.STM8L101xx ordering information scheme.76IntroductionSTM8L101xx8/84DocID15275 Rev 131 IntroductionThis datasheet provides the STM8L101xx pinout,ordering information,mechanical and electrical device characteristics.For complete information on the STM8L101xx microcontroller memory,registers and peripherals,please refer to the STM8L reference manual.The STM8L101xx devices are members of the STM8L low power 8-bit family.They arereferred to as low-density devices in the STM8L101xx microcontroller family reference manual(RM0013)and in the STM8L Flash programming manual(PM0054).All devices of the SM8L product line provide the following benefits:Reduced system costUp to 8 Kbytes of low-density embedded Flash program memory including up to 2 Kbytes of data EEPROMHigh system integration level with internal clock oscillators and watchdogs.Smaller battery and cheaper power supplies.Low power consumption and advanced featuresUp to 16 MIPS at 16 MHz CPU clock frequencyLess than 150 A/MH,0.8 A in Active-halt mode,and 0.3 A in Halt modeClock gated system and optimized power management Short development cyclesApplication scalability across a common family product architecture with compatible pinout,memory map and modular peripherals.Full documentation and a wide choice of development tools Product longevityAdvanced core and peripherals made in a state-of-the art technologyProduct family operating from 1.65 V to 3.6 V supply2 DescriptionThe STM8L101xx low power family features the enhanced STM8 CPU core providing increased processing power(up to 16 MIPS at 16 MHz)while maintaining the advantages of a CISC architecture with improved code density,a 24-bit linear addressing space and an optimized architecture for low power operations.The family includes an integrated debug module with a hardware interface(SWIM)which allows non-intrusive in-application debugging and ultrafast Flash programming.All STM8L101xx microcontrollers feature low power low-voltage single-supply program Flash memory.The 8-Kbyte devices embed data EEPROM.The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals.The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families.This makes any transition to a DocID15275 Rev 139/84STM8L101xxDescription22different family very easy,and simplified even more by the use of a common set of development tools.All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout.Table 2.Device featuresFeaturesSTM8L101xxFlash2 Kbytes of Flash program memory4 Kbytes of Flash program memory8 Kbytes of Flash program memory including up to 2 Kbytes of Data EEPROMRAM1.5 KbytesPeripheral functionsIndependent watchdog(IWDG),Auto-wakeup unit(AWU),Beep,Serial peripheral interface(SPI),Inter-integrated circuit(IC),Universal synchronous/asynchronous receiver/transmitter(USART),2 comparators,Infrared(IR)interfaceTimersTwo 16-bit timers,one 8-bit timerOperating voltage1.65 to 3.6 VOperating temperature-40 to+85 C-40 to+85 C or-40 to+125 CPackagesUFQFPN20 3x3UFQFPN28 4x 4UFQFPN20 3x3TSSOP20 4.4 x 6.4 UFQFPN28 4x4UFQFPN20 3x3UFQFPN32LQFP32Product overviewSTM8L101xx10/84DocID15275 Rev 133 Product overviewFigure 1.STM8L101xx device block diagram Legend:AWU:Auto-wakeup unit Int.RC:internal RC oscillator IC:Inter-integrated circuit multimaster interface POR/PDR:Power on reset/power down reset SPI:Serial peripheral interface SWIM:Single wire interface module USART:Universal synchronous/asynchronous receiver/transmitter IWDG:Independent watchdog?DocID15275 Rev 1311/84STM8L101xxProduct overview223.1 Central processing unit STM8The 8-bit STM8 core is designed for code efficiency and performance.It features 21 internal registers,20 addressing modes including indexed,indirect and relative addressing,and 80 instructions.3.2 Development toolsDevelopment tools for the STM8 microcontrollers include:The STice emulation system offering tracing and code profilingThe STVD high-level language debugger including C compiler,assembler and integrated development environmentThe STVP Flash programming softwareThe STM8 also comes with starter kits,evaluation boards and low-cost in-circuit debugging/programming tools.3.3 Single wire data interface(SWIM)and debug moduleThe debug module with its single wire data interface(SWIM)permits non-intrusive real-time in-circuit debugging and fast memory programming.The Single wire interface is used for direct access to the debugging module and memory programming.The interface can be activated in all device operation modes.The non-intrusive debugging module features a performance close to a full-featured emulator.Beside memory and peripherals,also CPU operation can be monitored in real-time by means of shadow registers.3.4 Interrupt controllerThe STM8L101xx features a nested vectored interrupt controller:Nested interrupts with 3 software priority levels26 interrupt vectors with hardware priorityUp to 29 external interrupt sources on 10 vectorsTrap and reset interruptsProduct overviewSTM8L101xx12/84DocID15275 Rev 133.5 MemoryThe STM8L101xx devices have the following main features:1.5 Kbytes of RAMThe EEPROM is divided into two memory arrays(see the STM8L reference manual for details on the memory mapping):Up to 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data EEPROM.Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism(MASS).64 option bytes(one block)of which 5 bytes are already used for the device.Error correction code is implemented on the EEPROM.3.6 Low power modesTo minimize power consumption,the product features three low power modes:Wait mode:CPU clock stopped,selected peripherals at full clock speed.Active-halt mode:CPU and peripheral clocks are stopped.The programmable wakeup time is controlled by the AWU unit.Halt mode:CPU and peripheral clocks are stopped,the device remains powered on.The RAM content is preserved.Wakeup is triggered by an external interrupt.3.7 Voltage regulatorsThe STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.This regulator has two different modes:main voltage regulator mode(MVR)and low power voltage regulator mode(LPVR).When entering Halt or Active-halt modes,the system automatically switches from the MVR to the LPVR in order to reduce current consumption.3.8 Clock controlThe STM8L101xx embeds a robust clock controller.It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes.This system clock is a 16-MHz High Speed Internal RC oscillator(HSI RC),followed by a programmable prescaler.In addition,a 38 kHz low speed internal RC oscill