bit-error-rate-analysis-of-cactus-technologies-sd-card-products(cactus-sd卡产品的比特误码速率分析—.doc

Bit Error Rate Analysis of Cactus Technologies SD Card Products 1.Introduction Cactus Technologies products are built using only the highest quality SLC (Single Level Cell) NAND flash devices. However, similar to hard disk media, NAND flash media is not perfect and soft errors will inevitably occur during usage. Various published papers have shown that the raw BER (Bit Error Rate) of SLC NAND is in the range of 1E9 to 1E11. While this is quite good and significantly better than that of MLC (Multi Level Cell) NAND, many pplications require BERs that are on par with, or better than those provided by traditional hard disk drives, which typically has BERs in the range of 1E15. Fortunately, the soft error mechanisms in SLC NAND are well understood and can be easily compensated for with the use of a robust ECC. In this paper, we will provide a brief analysis of the BER of Cactus SD Card products and show how the strong builtin ECC in the controller is able to provide typical application BERs that can match or even surpass that of typical hard disk drives. 2.The Problem Bit disturb phenomena is inherent to the NAND Cactus Technologies Limited ash architecture.There are three basic causes of such bit disturbs: Program disturb Read disturb Charge leakage Program disturb occurs when unselected cells are exposed to high voltages when neighboring cells are being programmed.The result of this inadvertent exposure to high voltages is that the affected cell appears slightly programmed. Read disturb occurs when unselected cells are exposed to normal operating voltages when neighboring cells are being read. The result of this is the affected cell appears slightly programmed.Due to the much lower voltages used during read operations, read disturb effects are much weaker than those of program disturb. Charge leakage occurs because the stored charge on the floating gate of the flash cell will slowly leak away over time, thus causing a programmed cell to gradually become unprogrammed. Fortunately, all three types of disturb mechanism described above are not permanent and the affected cells are restored once the block is erased. Therefore,to overcome the soft errors that are caused by these bit disturbs, all that is required is a sufficiently powerful ECC that is designed for the error characteristics of the flash media. 3.BER Analysis Cactus Technologies SD Cards employ a Reed Solomon code ECC capable of correcting 4 symbol errors over a 528 byte block.A simple mathematical analysis will show the improvement in BER that this ECC provides. In the following analysis, the variables are: P raw: raw bit error rate n : block size expressed as # of symbols t : # of correctable symbols P app: final application bit error rate P fail(n,i): probability of i errors in n symbols The probability of an uncorrectable error after ECC is applied is equal to the sum of the probabilities of at least t+1 errors. i.e. This sum can be approximated by the largest term, which is the probability of receiving exactly t+1 errors (since all the other terms are at least Praw less in probability). Thus, the final application bit error rate can be approximated by: where represents the number of possible permutations of t+1 symbols in n symbols. The last term is very nearly equal to 1, thus the final equation is approximately equal to the product of the permutation of t+1 in n multiplied by the raw BER to the power t+1. If we plot this equation using various values of t, we end up with a graph similar to the following: Note that while the graph above is for BCH codes, the difference between Reed Solomon codes and BCH codes in this application is small, as Reed Solomon codes are mathematically a special subset of BCH codes.This is evident in the following data presented by Micron Corporation:DesignedErrorCorrectionLevelTypical ApplicationBit Error RatesRead-SolomonBinaryBCHt=12.34e-152.34e-15t=27.69e-157.73e-15t=43.41e-153.47e-15t=63.59e-153.72e-15t=83.09e-153.28e-15It can be noted that from the theoretical calculation that we have presented and assuming the 3 basic soft error mechanisms in section 2 are the main source of errors, that the Reed Solomon ECC code in use in Cactus SD Card products is more than sufficient to bring the application BER to levels comparable to those in hard disk drives.The Micron data shows that inactual NAND flash devices, there are probably other sources of defects other than the 3 that we described in section 2, which presents a limit to the achievable improvement in BERs.Nonetheless, even with actual measured data as presented by Micron, the t=4 Reed Solomon code is still able to achieve a final BER better than 1E15. Most papers presented in the technical media has shown that for SLC NAND flash, a t=1 or t=2 ECC is more than sufficient to provide a final BER comparable to hard disk drives. 4.concludion We can therefore, safely conclude that Cactus Technologies SD Cards can achieve an application BER of 1E15 or better. Cactus SD卡产品的比特误码速率分析1、介绍单元测试原理技术的产品只建立在使用高质量的SLC（单层单元）NAND（非易失）技术的设备上。但是，它与磁盘媒体相类似。NAND技术是不完善的，而且软件错误会不可避免地发生在用法中。个别发表过的论文已经显示了SLC NAND技术的比特误码速率在1E-9到1E-11的范围内。而比起MLC（多层式储存单元）技术的误码率，这是相当好且明显更好的，在数值相同时，许多应用要求误码率，或许好过那些有传统硬盘驱动器规定的误码率。MLC通常有1E-15的误码率。幸运的是，这个SLC NAND里软件错误机制是容易理解和容易能用一个健全的ECC（错误检查和纠正）技术来补偿。在这篇论文中，我们将会提供一个关于Cactus SD卡产品误码率的简要分析，和展示ECC技术在控制中如何强壮地建立才能提供能够匹配的典型的应用误码率，甚至是超越典型的硬盘驱动器的误码率。2、问题比特“干扰”现象固有NAND技术被灰色的体系机构所限制。比特“干扰”现象的基本成因包括以下三个：编程干扰阅读干扰电荷泄露当邻近的单元正在被编排，未选中的单元被暴露在高压下时，编程干扰就会发生。这无意暴光高压的结果是受影响的单元出现些微的编程。当邻近的单元被读，未选中的单元被暴露在正常操作的电压时，阅读打扰就会发生。这样的结果是受影响的单元出现些微的编程。因为在阅读操作中出现过低的电压，阅读干扰的影响将比那些编程干扰弱得多。电荷泄露发生时因为被储存的电荷在浮栅的闪光单元讲会慢慢地随着时间的推移而漏出，从而导致一个编程单元渐渐成为未列入编程部分。幸运的是，三种干扰机制的类型以上描述的不是永久的，而且受影响的单元一旦一块被抹去就会“恢复”。因此，克服软件错误是由这些比特“干扰”造成的，一切被要求的是一个充分强大、被设计成误差特征闪光媒体？的ECC（错误检查和纠正）技术。3、误码速率分析Catus技术SD卡雇用一个Reed Slomon（里德所罗门）密码ECC（错误检查和纠正）技术，是一个能够纠正4个象征错误超过528个字节的ECC技术。一个简单的数学分析将会显示这个ECC技术在误码率中提供的重要性。在以下的分析中，变量是：P raw: 原比特误码率n : 块大小的符号表示为t : 符号的更正P app: 最终的应用误码率P fail(n,i): n个符号中i个错误的概率在ECC应用后的一个不可纠正的错误可能性等于t+1个错误总和的可能性。这个总和可以近似为最大项，这是精确接收t+1个错误的可能性（因为其他的所有项的可能性至少小于Praw）。因此，最终的应用比特错误率可以近似为：其中代表t+1个符号在n个符号中的可能排列数。最后项非常近似等于1，因此最后的方程近似等于t+1在n中的排列数乘以原比特错误率的t+1次。如果我们用t的各种值来绘制这个方程，就得出类似下面的一副图：注意，当上述图中是用BCH码时，里德所罗门码和BCH码在此应用上的差异是很小的，因为里德所罗门在数学上是一个特殊的BCH码.下表是由美光公司提供数据明显可以证明这一点：误差修正设计水平比特错误率的典型应用里德所罗门码BCH码t=12.34e-152.34e-15t=27.69e-157.73e-15t=43.41e-153.47e-15t=63.59e-153.72e-15t=83.09e-153.28e-15可以说，从理论上计算，我们已经提出和假设第2部分中的3个基本软件错误机制是错误的主要来源，因此里德所罗门ECC码在SD卡产品中的使用比在硬盘驱动器中能带来的比特错率水平更多。美光公司的数据显示：实际的NAND闪存器件有可能有其他的缺钱来源而不是我们在第2部分描述的那3种可能来源，他代表了一个比特错误率中可获得的改进的限制。但是，即时有了美光科技公司提供的实际测量数据，T= 4里德所罗门码仍然能够比1E-15取得更好的最后误码率。大多数在技术刊物上发表的论文都显示：对于SCL NAND闪存，t=1或者t=2的错误检查和纠正比硬盘驱动器等能够充分的提高最终的比特错误率。4.总结因此，我们可以安全的得出注意一个结论：仙人掌科技的SD卡可以更好的实现应用1E-15的比特误码率。