EDA教案(图和例题).doc

附 录
程序源码及实验设计参考：
1． 基本门电路实验
library ieee;
use ieee.std_logic_1164.all;

entity gate is
port (
signal a : in std_logic;
signal b: in std_logic;
signal y: out std_logic_vector(3 downto 0)
);
end gate;

architecture gate of gate is
begin
process(a,b)
begin
y(3)<=not a;
y(2)<=a and b;
y(1)<=a or b;
y(0)<=a xor b;
end process;
end gate;
2．3/8译码器实验
library ieee;
use ieee.std_logic_1164.all;

entity decoder is
port (
signal sel : in std_logic_vector (2 downto 0);
signal en: in std_logic;
signal y: out std_logic_vector(7 downto 0)
);
end decoder;

architecture behavior of decoder is
begin
process (sel,en)
begin
y<="11111111";
if (en='1') then
case sel is
when "000"=> y(0)<='0'; --0 bit of output is 0
when "001"=> y(1)<='0';
when "010"=> y(2)<='0';
when "011"=> y(3)<='0';
when "100"=> y(4)<='0';
when "101"=> y(5)<='0';
when "110"=> y(6)<='0';
when "111"=> y(7)<='0'; --7 bit of output is 0
when others=>null;
end case;
end if;
end process;
end behavior;
3．BCD/七段显示译码器实验
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity bcd is
port(d: in std_logic_vector(3 downto 0);
en: in std_logic;
data_out:out std_logic_vector(7 downto 0)
);
end bcd;

architecture bcd of bcd is
begin
process(d,en)
begin
if(en='1')then --signal enable
case d is
when"0000"=> data_out<="00111111"; --signal output:0
when"0001"=> data_out<="00000110";
when"0010"=> data_out<="01011011";
when"0011"=> data_out<="01001111";
when"0100"=> data_out<="01100110";
when"0101"=> data_out<="01101101";
when"0110"=> data_out<="01111101";
when"0111"=> data_out<="00000111";
when"1000"=> data_out<="01111111";
when"1001"=> data_out<="01100111"; --signal output:9
when others=> data_out<="11111111";
end case;
end if;
end process;
end bcd;
4．计数器实验
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(
signal reset:in std_logic;
signal en:in std_logic;
signal clk:in std_logic;
signal clk_out:out std_logic
);
end counter;

architecture behavior of counter is
signal count:integer range 0 to 9;
begin
process(clk,en)
begin

if clk'event and clk='1' then
if reset='1' then
clk_out<='0';
count<=0;
elsif en='1' then
if count<9 then
count<=count+1;
clk_out<='0';
else
count<=0;
clk_out<='1';
end if;
end if;
end if;
end process;
end behavior;

5．模拟74ls160计数器实验
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lscounter is
port (
signal cp,mr,cep,cet,pe: in std_logic;
signal d: in std_logic_vector(3 downto 0);
signal tc: out std_logic:='0' ;
signal q: buffer std_logic_vector(3 downto 0):="0000"
);
end lscounter;

architecture behavior of lscounter is
begin
process(mr,cp,cep,pe,cet)
begin

if(mr='0')then --judge singal mr
q<="0000"; --reset
tc<='0';
elsif cp'event and cp='1' then
if pe='0' then --judge signal pe
q<=d; --set q
if d>="1001" then
q<=q;
tc<='1';
end if;
elsif cet='0' then --output q hold
q<=q;
tc<='0';
elsif cep='0' then
q<=q;
if q="1001" then
q<="0000";
tc<='1';
end if;
else

q<=q+1; --count
tc<='0';
if q="1001" then --set counting range
q<="0000";
tc<='1';
end if;
end if;
else null;
end if;
end process;
end behavior;
6．交通灯控制器
library ieee;
use ieee.std_logic_1164.all;
entity trflight is
port (
signal ra,ya,ga,rb,yb,gb: out std_logic :='0';
signal clk: in std_logic
);
end trflight;

architecture behavior of trflight is
type state is(no1,no2,no3,no4,no5,no6,no7,no8);
signal current_state :state:=no1;
begin
process (clk)
begin
if clk'event and clk='1' then
case current_state is
when no1 =>ra<='1';ya<='0';ga<='0';rb<='0';yb<='0';gb<='1';
current_state<=no2;
when no2 =>ra<='1';ya<='0';ga<='0';rb<='0';yb<='1';gb<='0';
current_state<=no3;
when no3 =>ra<='0';ya<='1';ga<='0';rb<='0';yb<='1';gb<='0';
current_state<=no4;
when no4 =>ra<='0';ya<='1';ga<='0';rb<='1';yb<='0';gb<='0';
current_state<=no5;
when no5 =>ra<='0';ya<='0';ga<='1';rb<='1';yb<='0';gb<='0';
current_state<=no6;
when no6 =>ra<='0';ya<='1';ga<='0';rb<='1';yb<='0';gb<='0';
current_state<=no7;
when no7 =>ra<='0';ya<='1';ga<='0';rb<='0';yb<='1';gb<='0';
current_state<=no8;
when no8 =>ra<='1';ya<='0';ga<='0';rb<='0';yb<='1';gb<='0';
current_state<=no1;
when others=>current_state<=no1;
end case;
else null;
end if;
end process;
end behavior;
7．乒乓球游戏机
library ieee;
use ieee.std_logic_1164.all;

entity pingpang is
port(
signal reset:in std_logic;
signal locate:buffer std_logic_vector(5 downto 0);
signal clk:in std_logic;
signal awin,bwin:out std_logic;
signal a,b :in std_logic
);
end pingpang;

architecture behavior of pingpang is
type state is(no0,no1,no2,no3,no4,no5,no6,no7);
signal current_state:state:=no0;
signal direction :std_logic;
begin

process(clk)
begin
if clk'event and clk='1' then
case current_state is --judge current_state
when no0=>direction<='0'; --judge direction:0 from a to b; 1 from b to a
locate(0)<='0';
locate(1)<='0';
locate(2)<='0';
locate(3)<='0';
locate(4)<='0';
locate(5)<='0';
bwin<='1';awin<='0'; --signal bwin output
if reset='1' then --judge signal reset: 0 reset
current_state<=no1;
else
current_state<=no0; --reset
end if;
when no1=>locate(0)<='1'; --locate 1
locate(1)<='0';
locate(2)<='0';
locate(3)<='0';
locate(4)<='0';
locate(5)<='0';
awin<='0';bwin<='0';
if(direction='0') then --judge direction
if b='0' then --judge whether b hits
current_state<=no0;
else
current_state<=no2;
end if;
else
if a='0' then --judge whether a hits
current_state<=no2;
direction<='0'; --reverse direction

else
current_state<=no0;
end if;
end if;
when no2=>locate(0)<='0'; --locate 2
locate(1)<='1';
locate(2)<='0';
locate(3)<='0';
locate(4)<='0';
locate(5)<='0';
awin<='0';bwin<='0';
if(direction='0') then
if b='0' then
current_state<=no0;
else
current_state<=no3;
end if;
else
if a='0' then
current_state<=no3;
direction<='0';
else
current_state<=no1;
end if;
end if;
when no3=>locate(0)<='0'; --locate 3
locate(1)<='0';
locate(2)<='1';
locate(3)<='0';
locate(4)<='0';
locate(5)<='0';
awin<='0';bwin<='0';
if(direction='0') then
if b='0' then
current_state<=no0;
else
current_state<=no4;
end if;
else
if a='0' then
current_state<=no4;
direction<='0';
else
current_state<=no2;
end if;
end if;
when no4=>locate(0)<='0'; --locate 4
locate(1)<='0';
locate(2)<='0';
locate(3)<='1';
locate(4)<='0';
locate(5)<='0';
awin<='0';bwin<='0';
if(direction='1') then
if a='0' then
current_state<=no7;
else
current_state<=no3;
end if;
else
if b='0' then
current_state<=no3;
direction<='1';
else
current_state<=no5;
end if;
end if;
when no5=>locate(0)<='0'; --locate 5
locate(1)<='0';
locate(2)<='0';
locate(3)<='0';
locate(4)<='1';
locate(5)<='0';
awin<='0';bwin<='0';
if(direction='1') then
if a='0' then
current_state<=no7;
else
current_state<=no4;
end if;
else
if b='0' then
current_state<=no4;
direction<='1';
else
current_state<=no6;
end if;
end if;
when no6=>locate(0)<='0'; --locate 6
locate(1)<='0';
locate(2)<='0';
locate(3)<='0';
locate(4)<='0';
locate(5)<='1';
awin<='0';bwin<='0';
if(direction='1') then
if a='0' then
current_state<=no7;
else
current_state<=no5;
end if;
else
if b='0' then
current_state<=no5;
direction<='1';
else
current_state<=no7;
end if;
end if;
when no7=>direction<='1'; --reverse direction
locate(0)<='0';
locate(1)<='0';
locate(2)<='0';
locate(3)<='0';
locate(4)<='0';
locate(5)<='0';
awin<='1';bwin<='0';
if reset='1' then
current_state<=no6;
else
current_state<=no7;
end if;
when others=>locate<="000000";
current_state<=no0;
end case;
end if;
end process;
end behavior;
8．扫描数码显示器

led源代码如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity led is
port(d0: in std_logic_vector(3 downto 0);
d1: in std_logic_vector(3 downto 0);
d2: in std_logic_vector(3 downto 0);
d3: in std_logic_vector(3 downto 0);
d4: in std_logic_vector(3 downto 0);
d5: in std_logic_vector(3 downto 0);
sel_bcd: in std_logic_vector(2 downto 0);
data_out:out std_logic_vector(3 downto 0)
);
end led;

architecture led of led is
begin
process
begin
case sel_bcd is
when"000"=> data_out<=d0; --channel 1 to 6
when"001"=> data_out<=d1;
when"010"=> data_out<=d2;
when"011"=> data_out<=d3;
when"100"=> data_out<=d4;
when"101"=> data_out<=d5;
when others=>null;

end case;
end process;
end led;

counter在此为六进制计数器：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(
signal reset:in std_logic;
signal en:in std_logic;
signal clk:in std_logic;
signal clk_out:out std_logic;
signal count:buffer std_logic_vector(2 downto 0)

);
end counter;

architecture behavior of counter is

begin
process(clk)
begin

if clk'event and clk='1' then
if reset='1' then
clk_out<='0';
count<="000";
elsif en='1' then
if count<"101" then
count<=count+1;
clk_out<='0';
else
count<="000";
clk_out<='1';
end if;
end if;
end if;

end process;
end behavior;