FPGA底层代码,正弦波,方波,三角波,锯齿波.doc

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一．频率控制模块代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FREQUENCY IS PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);--设置A的初值 FOUT : OUT STD_LOGIC ); END; ARCHITECTURE one OF FREQUENCY IS SIGNAL FULL : STD_LOGIC; BEGIN P_REG: PROCESS(CLK) VARIABLE CNT1 : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN IF CLK'EVENT AND CLK = '1' THEN IF CNT1 = "11111" THEN CNT1 := A; --当CNT1计数计满时，输入数据D被同步预置给计数器 CNT1 FULL <= '1'; --同时使溢出标志信号FULL输出为高电平 ELSE CNT1 := CNT1 + 1; --否则继续作加1计数 FULL <= '0'; --且输出溢出标志信号FULL为低电平 END IF; END IF; END PROCESS P_REG P_DIV: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN IF FULL'EVENT AND FULL = '1' THEN CNT2 := NOT CNT2; --如果溢出标志信号FULL为高电平，D触发器输出取反 IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF; END PROCESS P_DIV END; 二．按键选择模块代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BUTTON IS PORT ( d : IN STD_LOGIC_VECTOR(2 DOWNTO 0) a,b,c : OUT STD_LOGIC ) END; ARCHITECTURE ONE OF BUTTON IS BEGIN PROCESS( d ) BEGIN CASE d IS WHEN "000" => NULL; WHEN OTHERS => a <= d(0);--dlt b <= d(1);--sqr c <= d(2);--sin END CASE; END PROCESS; END; 三角波信号产生模块代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity delta is port ( clk : in std_logic clr : in std_logic; q : out std_logic_vector(7 downto 0) ) end delta; architecture one of delta is begin process( clk,clr) variable num : std_logic_vector(7 downto 0); variable ff : std_logic; begin if clr = '0' then num := "00000000"; else if clk'event and clk = '1' then--时钟信号有上升沿时有效 if ff = '0' then if num = "11111000" then ff :='1'; else num := num + 8; end if;--以上，ff=0时，上升，直至num加到11111000时，使ff=1 else if num = "00000111" then num := "00000000"; ff := '0'; else num := num -8;--以上，ff=1时，下降，直至num减到00000111时，使ff=0 end if; end if; end if; end if; q <= num;--每一次脉冲，将num的值给q以输出 end process end; 四．方波信号产生模块代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity aquare is port ( clk : in std_logic clr : in std_logic; q : out std_logic_vector(7 downto 0) ) end aquare; architecture one of aquare is signal ff:bit; begin p1:process( clk,clr) variable num : std_logic_vector(5 downto 0); begin if clr = '0' then ff <= '0'; else if clk'event and clk = '1' then--当时钟脉冲有一个上升沿 if num < 31 then num := num+1; else num := "000000"; ff <= not ff;--num每次加1，加32次ff取反1次 end if; end if; end if; end process p1; p2: process( clk,ff) begin if clk'event and clk = '1' then if ff = '1' then q <= "11111111";--ff=1时输出高电平 else q <= "00000000";--ff=0时输出低电平 end if; end if; end process p2; end; 五．正弦波信号产生模块代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sin is port ( clk : in std_logic --正弦信号的相位 clr : in std_logic; d : out std_logic_vector(7 downto 0) ) --正弦函数值 end architecture one of sin is--结构体开始 Begin process( clk,clr) variable num : std_logic_vector(5 downto 0); Begin if clr = '0' then d <= "00000000"; else if clk'event and clk = '1' then if num = "111111" then num := "000000";--每加到111111时清零 else num := num+1; end if; end if; end if; case num is --四个输入，共有16总相位可能 360/64=5.625 when "000000" => d <= CONV_STD_LOGIC_VECTOR(128,8); --每5.625取一个点 when "000001" => d <= CONV_STD_LOGIC_VECTOR(141,8); --共64个点 when "000010" => d <= CONV_STD_LOGIC_VECTOR(153,8); when "000011" => d <= CONV_STD_LOGIC_VECTOR(165,8); when "000100" => d <= CONV_STD_LOGIC_VECTOR(177,8); when "000101" => d <= CONV_STD_LOGIC_VECTOR(188,8); when "000110" => d <= CONV_STD_LOGIC_VECTOR(199,8); when "000111" => d <= CONV_STD_LOGIC_VECTOR(209,8); when "001000" => d <= CONV_STD_LOGIC_VECTOR(218,8); when "001001" => d <= CONV_STD_LOGIC_VECTOR(227,8); when "001010" => d <= CONV_STD_LOGIC_VECTOR(234,8); when "001011" => d <= CONV_STD_LOGIC_VECTOR(240,8); when "001100" => d <= CONV_STD_LOGIC_VECTOR(246,8); when "001101" => d <= CONV_STD_LOGIC_VECTOR(250,8); when "001110" => d <= CONV_STD_LOGIC_VECTOR(253,8); when "001111" => d <= CONV_STD_LOGIC_VECTOR(254,8); when "010000" => d <= CONV_STD_LOGIC_VECTOR(255,8); when "010001" => d <= CONV_STD_LOGIC_VECTOR(254,8); when "010010" => d <= CONV_STD_LOGIC_VECTOR(253,8); when "010011" => d <= CONV_STD_LOGIC_VECTOR(250,8); when "010100" => d <= CONV_STD_LOGIC_VECTOR(246,8); when "010101" => d <= CONV_STD_LOGIC_VECTOR(240,8); when "010110" => d <= CONV_STD_LOGIC_VECTOR(234,8); when "010111" => d <= CONV_STD_LOGIC_VECTOR(227,8); when "011000" => d <= CONV_STD_LOGIC_VECTOR(218,8); when "011001" => d <= CONV_STD_LOGIC_VECTOR(209,8); when "011010" => d <= CONV_STD_LOGIC_VECTOR(199,8); when "011011" => d <= CONV_STD_LOGIC_VECTOR(188,8); when "011100" => d <= CONV_STD_LOGIC_VECTOR(177,8); when "011101" => d <= CONV_STD_LOGIC_VECTOR(165,8); when "011110" => d <= CONV_STD_LOGIC_VECTOR(153,8); when "011111" => d <= CONV_STD_LOGIC_VECTOR(141,8); when "100000" => d <= CONV_STD_LOGIC_VECTOR(128,8); when "100001" => d <= CONV_STD_LOGIC_VECTOR(115,8); when "100010" => d <= CONV_STD_LOGIC_VECTOR(103,8); when "100011" => d <= CONV_STD_LOGIC_VECTOR(91,8); when "100100" => d <= CONV_STD_LOGIC_VECTOR(79,8); when "100101" => d <= CONV_STD_LOGIC_VECTOR(68,8); when "100110" => d <= CONV_STD_LOGIC_VECTOR(57,8); when "100111" => d <= CONV_STD_LOGIC_VECTOR(47,8); when "101000" => d <= CONV_STD_LOGIC_VECTOR(38,8); when "101001" => d <= CONV_STD_LOGIC_VECTOR(29,8); 六．波形选择器代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity changer is port ( dlt,sqr,sin : in std_logic dltd,sqrd,sind : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0) ) end changer; architecture one of changer is Begin process( dlt,dltd,sqr,sqrd,sin,sind) variable temp : std_logic_vector(2 downto 0); -- variable a,b : std_logic_vector(9 downto 0); -- variable c,d,e : std_logic_vector(9 downto 0); Begin temp :=dlt&sqr&sin; case temp is when "100" => q <= dltd;--a00输出三角波 when "010" => q <= sqrd;--0b0输出方波 when "001" => q <= sind;--00c输出正弦波 when others => null; end case; end process end;

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