主板时钟信号量测.pptx

Clock Measurement SkillDate:2017/07Agenda1.Power2.Crystal Clock3.Clock，DDR CLK，PCI CLK，Low Frequency Clock POWER1.1.量測表格量測表格 :PowerCKW1NET NAMEVCC3FigureFigSPECMAX:3.465MIN:3.135STATUS STATUS UNITVPOWERPOWER將將position scale 儘量調小儘量調小 將將resolution scale調整至調整至200s 開開bandwidth:20MHz 注意調整注意調整offset使量測圖形集中於屏幕中間使量測圖形集中於屏幕中間量測量測max,min,mean值值Position 點儘量調到整格線點儘量調到整格線記得加上記得加上label跑跑3000筆以上筆以上Crystal Clock1.1.量測表格量測表格 :Crystal ClockCKC1NET NAME32KHz(Y6)FigureFigTYPEFreqSPECMAX:32.768655MIN:32.767344STATUSUNITKHzMeasure VoltageRise Time=，Fall Time=High Time=Low Time=Jitter=，Cross Voltage=NOTE：(-10ppm)CKC2NET NAME25MHz(Y5)FigureFigTYPEFreqSPECMAX:25.00075MIN:24.99925STATUSUNITMHzMeasure VoltageRise Time=，Fall Time=High Time=Low Time=Jitter=，Cross Voltage=NOTE：Crystal Clock20X32.768/1000000=0.000655Max=32.768+0.000655=32.768655Min=32.7680.000655=32.767344補充：1.Frequency tolerance 請參照spec或是零件承證書。2.接上電源處於待機模式量測。3.若無法截取頻率 則開機進入BIOS模式量測（PCH、CLOCK GEN）或是接上網路線（LAN）。Crystal ClockCrystal ClockFrequency CounterClock1.1.量測表格量測表格 :CKH9 NET NAMECK_PBG_CLKINITEMABCDEFFigureFigFig Fig FigFigFigTYPEFreqRise timeFall timeLow timeHigh timeJitterSPEC100MAX:4MAX:4MAX:5.5MAX:5.5MAX:50MIN:1MIN:1MIN:4.5MIN:4.5MIN:-50STATUS STATUS UNITMHzV/nsV/nsnsnspsMeasure VoltageFreq=RiseFall Time:High Time=Cross Voltage Point；Low Time=Cross Voltage Point；Jitter=High refernece 75%Low reference 25%；Cross Voltage=NOTE：Duty Cycle:45%55%jitter:ICS9FG1200-5Spec 參照方式以終端為主，發送端為副如果終端找不到SPEC則往前一階找CLK GENPCHSIO(SIO SPEC)如果SIO找不到則找PCH，如果PCH找不到才找CLK GEN.Main clock signal in mother-boardClock Gen Differential/Single ClockHigh Frequency Differential ClockLow Frequency-Single ClockClockClockCKH9 NET NAMECK_PBG_CLKINITEMABCDEFFigureFigFig Fig FigFigFigTYPEFreqRise timeFall timeLow timeHigh timeJitterSPEC100MAX:4MAX:4MAX:5.5MAX:5.5MAX:50MIN:1MIN:1MIN:4.5MIN:4.5MIN:-50STATUS STATUS UNITMHzV/nsV/nsnsnspsMeasure VoltageFreq=RiseFall Time:High Time=Cross Voltage Point；Low Time=Cross Voltage Point；Jitter=High refernece 75%Low reference 25%；Cross Voltage=NOTE：Duty Cycle:45%55%jitter:ICS9FG1200-5Frequency取最小取最小值值、最大值、最大值累積500筆資料)Rise&Fall timeRise&Fall time（續）（續）Rise&Fall time（續）（續）High&Low timeJitter設要量測的設要量測的channel1.Jitter：有些是示波器是有些是示波器是 FilesRun applicationjitter analysis3 Jitter數值調整到數值調整到2525左右左右調整完後執行調整完後執行量測量測Jitter時要記得關掉累積時要記得關掉累積,且要跑且要跑1000筆以上筆以上 DDR Clock1.1.量測表格量測表格 :1.SPEC:JEDEC Standard2.量測點在RAM上DDR ClockDDR III Schematic IntroductionAddressDataVrefClockCross Voltage Cross Voltage 設要量測的設要量測的channel1.Jitter：有有些些是是示示波波器器是是 FilesRun applicationjitter analysis3 Cross Voltage 量測CrossVoltage時要記得關掉累積,且要跑200筆以上 調整調整resolution resolution 至最精密至最精密調整完後執行調整完後執行讓波形彼此互相交叉3個點PCI CLK1.量測表格量測表格:PCI CLKPCI CLK將橫向的將橫向的SCALE調整到只有一個完整的調整到只有一個完整的rise edge b.量测量测Rising time依依spec設定設定Rise Time=0.66V-1.98V，Fall Time=0.66V-1.98V Pci Spec-Max:4 V/ns;Min:1 V/ns (1.98-0.66)/t=4,t=0.33ns,(1.98-0.66)/t=1,t=1.32nsPCI CLK將橫向的將橫向的SCALE調整到只有一個完整的調整到只有一個完整的 fall edge c.量测量测Falling time依依spec設定設定PCI CLKd.量测量测Low time調整到只有一個完整的調整到只有一個完整的Low time 依依spec設定設定PCI CLK調整到只有一個完整的調整到只有一個完整的 Hi time 依依spec設定設定e.量测量测High timeLow Frequency ClockLow frequency clockLow frequency clockNONOCKL1CKL1NET NAMENET NAME14M_ICH14M_ICHITEMITEMA AB BC CDDE EFigureFigureFigFigFigFigFigFigFigFigFigFigTYPETYPEFreqFreqRise timeRise timeFall timeFall timeLow timeLow timeHigh timeHigh timeSPECSPEC1414Max:1.2Max:1.2Max:1.2Max:1.2Min:20Min:20Min:20Min:20Min:0.3Min:0.3Min:0.3Min:0.3STATUSSTATUSSTATUSSTATUSUNITUNITMHzMHznsnsnsnsnsnsnsnsMeasure VoltageMeasure VoltageRise Time=0.8V-2.0VRise Time=0.8V-2.0V，Fall Time=0.8V-2.0V Spec-Max:4 V/ns;Min:1 V/ns Fall Time=0.8V-2.0V Spec-Max:4 V/ns;Min:1 V/ns (2-0.8)/t=4,t=0.3ns,(2-0.8)/t=1,t=1.2ns(2-0.8)/t=4,t=0.3ns,(2-0.8)/t=1,t=1.2nsHigh Time=2VHigh Time=2V，Low Time=0.8VLow Time=0.8VNOTENOTE：測試方法與PCI相同，注意終端SPEC