组成原理实验报告-—基于硬布线控制器设计并实现-学位论文.doc

计算机组成原理实验报告
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实验报告

实验名称：
基于硬布线控制器设计并实现
带中断功能的复杂模型机
日期：
2011-1-12

班级：

学号：

姓名：

一、实验目的：
1.
掌握硬布线控制器的组成原理、设计方法；
2.
了解硬布线控制器和微程序控制器的各自优缺点；
3.
掌握并会设计带中断功能的复杂模型机的硬布线控制器。

二、实验内容：
1.
根据带中断功能的复杂模型机的微程序流图，画出状态机描述图；
2.
分析每个状态所需的控制信号，产生控制信号表，并用VHDL语言来设计程序，实现状态机描述的功能；
3.
用Quartus软件进行编译链接，选择器件，定义管脚，编程下载，然后用CM3P联机测试每一条机器指令的功能。

三、项目要求及分析：
实验要求设计带中断功能的复杂模型机的硬布线控制器，可先参照前面带中断处理能力的模型机设计实验画出微程序流程图，参照二进制微代码表设控制信号表。然后用VHDL语言编程实现，主要注意原P<1>—P<4>的修改，采用分支语句实现。然后就是连线装载带中断处理能力的模型机微程序检验。

四、具体实现：
应包括：状态图、控制信号表、控制引脚图、VHDL程序、机器码验证程序等。
1、状态图：
2、控制状态表：
INTA/WR/RD/IOM/S3/S2/S1/S0/LDA/LDB/LDR0/LDSP/L0AD/LDAR/LDIR/ALUB/RSB/RDB/RIB/SPB/PCB/LDPC/STI/CLI
S0 100000000000100111111010
S1 100000000000100111111011
S2 100000000000110111110111
S3 101000000000101111111011
S4 100000000100100101111011
S5 100010010010100011111011
S6 100000000100100101111011
S7 100000100010100011111011
S8 101000000000110111111011
S9 101100000010100111111011
S10 101000000000110111111011
S11 100000000000100111111011
S12 101000000010100111111011
S13 110000000000100110111011
S14 100000000000000011111111
S15 100000000000100111111011
S16 110100000000100101111011
S17 101000000010100111111011
S18 110000000000100101111011
S19 100000001000100111101011
S20 100011010001100011111011
S21 100011000001100011111011
S22 100000000000110111101011
S23 101000000010100111111011
S24 100011000001100011111011
S25 100000000000110111101011
S26 101000000000000111111111
S27 100000000000000011111111
S28 101000001000100111111011
S29 101000000000110111111011
S30 101000000000110111111011
S31 101000001000100111111011
S32 101000000000110111111011
S33 000000000000110111101011
S34 110000000000100111110011
S35 100000001000100111101011
S36 100011010001100011111011
S37 000000000000110111111011
S38 101000000000000111111111
S39 101000001000100111111011
S40 100000000100100111011011
S41 100010010000110011111011
S42 100010011000100011111011
S43 101000001000100111111011
S44 100000000100100111110011
S45 100010010000110011111011
S46 100010011000100011111011
S47 100000001000100110111011
S48 100000001000100110111011
S49 100000000000110111110111
S50 100000000000110111110111
S51 100000000010100101111011
S52 100000000000100111111011
S53 100000000000110111110111
S54 100000000000100111111001
S55 100000000000100111111010
S56 100000000000110111101011
S57 100000001000100111101011
S58 100000001000100111101011
S59 100000000000110111110111
S60 100000000000110111110111
S61 100000000000110111110111
S62 100000000000110111110111
3、控制引脚图：

五、调试运行结果：

4、VHDL程序：
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY CONTROLLER IS
PORT(
RESET : IN STD_LOGIC;
T1 : IN STD_LOGIC;
INTR : IN STD_LOGIC;
INS : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CTRL : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END CONTROLLER;

ARCHITECTURE CONTROLLER_ARCH OF CONTROLLER IS
TYPE STATE IS (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,
S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,
S36,S37,S38,S39,S40,S41,S42,S43,S44,S45,S46,S47,S48,S49,S50,S51,S52,S53,S54,
S55,S56,S57,S58,S59,S60,S61,S62);
SIGNAL CUFSM: STATE;

--CTRL:INTA,WR,RD,IOM,S3,S2,S1,S0,LDA,LDB,LDRI,LDSP,LOAD,LDAR,LDIR,ALU_B,RS_B,RD_B,RI_B,SP_B,PC_B,LDPC,STI,CLI
BEGIN
PROCESS (T1,RESET,INTR,INS)
BEGIN
IF RESET = '0' THEN
CTRL <= "100000000000100111111010"; --CLI
CUFSM <= S0;
ELSIF T1'EVENT AND T1 = '1' THEN
CASE CUFSM IS
WHEN S0 =>
CTRL <= "100000000000100111111011"; --中断判断
CUFSM <= S1;
WHEN S1 =>
IF INTR='1' THEN
CTRL <= "000000000000110111101011"; --R0->BUS,BUS->A
CUFSM <= S33;
ELSE CTRL <= "100000000000110111110111";
CUFSM <= S2;
END IF;

WHEN S33=>
CTRL <= "110000000000100111110011";
CUFSM <= S34;

WHEN S34=>
CTRL <= "100000001000100111101011";
CUFSM <= S35;

WHEN S35=>
CTRL <= "100011010001100011111011";
CUFSM <= S36;

WHEN S36=>
CTRL <= "000000000000110111111011";
CUFSM <= S37;

WHEN S37=>
CTRL <= "101000000000000111111111";
CUFSM <= S38;
WHEN S38=>
CTRL <= "100000000000110111110111";
CUFSM <= S2;
WHEN S2=>
CTRL <= "101000000000101111111011";
CUFSM <= S3;
WHEN S3 =>
IF INS(7 downto 4) = "0000" THEN --ADD INS
CTRL <= "100000001000100110111011";
CUFSM <= S47;
ELSIF INS(7 downto 4) = "0001" THEN --AND INS
CTRL <= "100000001000100110111011";
CUFSM <= S48;
ELSIF INS(7 downto 4) = "0010" THEN -- IN INS
CTRL <= "100000000000110111110111";
CUFSM <= S49;
ELSIF INS(7 downto 4) = "0011" THEN --OUT INS
CTRL <= "100000000000110111110111";
CUFSM <= S50;
ELSIF INS(7 downto 4) = "0100" THEN -- MOV INS
CTRL <= "100000000010100101111011";
CUFSM <= S51;
ELSIF INS(7 downto 4) = "0101" THEN -- HLT INS
CTRL <= "100000000000100111111011";
CUFSM <= S52;
ELSIF INS(7 downto 4) = "0110" THEN -- LDI INS
CTRL <= "100000000000110111110111";
CUFSM <= S53;
ELSIF INS(7 downto 4)= "0111" THEN -- STI INS
CTRL <= "100000000000100111111001";
CUFSM <= S54;
ELSIF INS(7 downto 4) = "1000" THEN -- CLI INS
CTRL <= "100000000000100111111010";
CUFSM <= S55;
ELSIF INS(7 downto 4) = "1001" THEN -- PUSH INS
CTRL <= "100000000000110111101011";
CUFSM <= S56;
ELSIF INS(7 downto 4) = "1010" THEN -- POP INS
CTRL <= "100000001000100111101011";
CUFSM <= S57;
ELSIF INS(7 downto 4) = "1011" THEN -- INET INS
CTRL <= "100000001000100111101011";
CUFSM <= S58;
ELSIF INS(7 downto 6) = "11" AND INS(3 downto 2) = "00" THEN -- 直接 INS
CTRL <= "100000000000110111110111";
CUFSM <= S59;
ELSIF INS(7 downto 6) = "11" AND INS(3 downto 2) = "01" THEN -- 间接 INS
CTRL <= "100000000000110111110111";
CUFSM <= S60;
ELSIF INS(7 downto 6) = "11" AND INS(3 downto 2) = "10" THEN -- 变址 INS
CTRL <= "100000000000110111110111";
CUFSM <= S61;
ELSIF INS(7 downto 6) = "11" AND INS(3 downto 2) = "11" THEN -- 相对 INS
CTRL <= "100000000000110111110111";
CUFSM <= S62;
END IF;
WHEN S47=>
CTRL <= "100000000100100101111011";
CUFSM <= S4;
WHEN S4=>
CTRL <= "100010010010100011111011";
CUFSM <= S5;
WHEN S5=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S48=>
CTRL <= "100000000100100101111011";
CUFSM <= S6;
WHEN S6 =>
CTRL <= "100000100010100011111011";
CUFSM <= S7;
WHEN S7=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S49=>
CTRL <= "101000000000110111111011";
CUFSM <= S8;
WHEN S8=>
CTRL <= "101100000010100111111011";
CUFSM <= S9;
WHEN S9=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S50=>
CTRL <= "101000000000110111111011";
CUFSM <= S10;
WHEN S10=>
CTRL <= "110100000000100101111011";
CUFSM <= S16;
WHEN S16=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S51=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S52=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S53=>
CTRL <= "101000000010100111111011";
CUFSM <= S17;
WHEN S17=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S54=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S55=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S56=>
CTRL <= "110000000000100101111011";
CUFSM <= S18;
WHEN S18=>
CTRL <= "100000001000100111101011";
CUFSM <= S19;
WHEN S19=>
CTRL <= "100011010001100011111011";
CUFSM <= S20;
WHEN S20=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S57=>
CTRL <= "100011000001100011111011";
CUFSM <= S21;
WHEN S21=>
CTRL <= "100000000000110111101011";
CUFSM <= S22;
WHEN S22=>
CTRL <= "101000000010100111111011";
CUFSM <= S23;
WHEN S23=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S58=>
CTRL <= "100011000001100011111011";
CUFSM <= S24;
WHEN S24=>
CTRL <= "100000000000110111101011";
CUFSM <= S25;
WHEN S25=>
CTRL <= "101000000000000111111111";
CUFSM <= S26;
WHEN S26=>
CTRL <= "100000000000100111111011";
CUFSM <= S1;
WHEN S59=>
CTRL <= "101000001000100111111011";
CUFSM <= S28;
WHEN S28=>
CTRL <= "101000000000110111111011";
CUFSM <= S29;
WHEN S60=>
CTRL <= "101000000000110111111011";
CUFSM <= S30;
WHEN S30=>
CTRL <= "101000001000100111111011";
CUFSM <= S31;
WHEN S31=>
CTRL <= "101000000000110111111011";
CUFSM <= S32;
WHEN S61 =>
CTRL <= "101000001000100111111011";
CUFSM <= S39;
WHEN S39 =>
CTRL <= "100000000100100111011011";
CUFSM <= S40;
WHEN S40 =>
CTRL <= "100010010000110011111011";
CUFSM <= S41;
WHEN S41 =>
CTRL <= "100010011000100011111011";
CUFSM <= S42;
WHEN S62 =>
CTRL <= "101000001000100111111011";
CUFSM <= S43;
WHEN S43 =>
CTRL <= "100000000100100111110011";
CUFSM <= S44;
WHEN S44 =>
CTRL <= "100010010000110011111011";
CUFSM <= S45;
WHEN S45 =>
CTRL <= "100010011000100011111011";
CUFSM <= S46;
WHEN S29=>
IF INS(7 downto 4) = "1100" THEN
CTRL <= "101000000010100111111011";
CUFSM <= S12;
ELSIF INS(7 downto 4) = "1101" THEN
CTRL <= "110000000000100110111011";
CUFSM <= S13;
ELSIF INS(7 downto 4) = "1110" THEN
CTRL <= "100000000000000011111111";
CUFSM <= S14;
ELSIF INS(7 downto 4) = "1111" THEN
CTRL <= "100000000000100111111011";
CUFSM <= S15;
END IF;
WHEN S32=>
IF INS(7 downto 4) = "1100" THEN
CTRL <= "101000000010100111111011";
CUFSM <= S12;
ELSIF INS(7 downto 4) = "1101" THEN
CTRL <= "110000000000100110111011";
CUFSM <= S13;
ELSIF INS(7 downto 4) = "1110" THEN
CTRL <= "100000000000000011111111";
CUFSM <= S14;
ELSIF INS(7 downto 4) = "1111" THEN
CTRL <= "100000000000100111111011";
CUFSM <= S15;
END IF;
WHEN S42 =>
IF INS(7 downto 4) = "1100" THEN
CTRL <= "101000000010100111111011";
CUFSM <= S12;
ELSIF INS(7 downto 4) = "1101" THEN
CTRL <= "110000000000100110111011";
CUFSM <= S13;
ELSIF INS(7 downto 4) = "1110" THEN
CTRL <= "100000000000000011111111";
CUFSM <= S14;
ELSIF INS(7 downto 4) = "1111" THEN
CTRL <= "100000000000100111111011";
CUFSM <= S15;
END IF;
WHEN S46 =>
IF INS(7 downto 4) = "1100" THEN
CTRL <= "101000000010100111111011";
CUFSM <= S12;
ELSIF INS(7 downto 4) = "1101" THEN
CTRL <= "110000000000100110111011";
CUFSM <= S13;
ELSIF INS(7 downto 4) = "1110" THEN
CTRL <= "100000000000000011111111";
CUFSM <= S14;
ELSIF INS(7 downto 4) = "1111" THEN
CTRL <= "100000000000100111111011";
CUFSM <= S15;
END IF;

WHEN S12=>
CTRL <= "100000000000100111111011"; --R0->BUS,BUS->B
CUFSM <= S1;
WHEN S13=>
CTRL <= "100000000000100111111011"; --R0->BUS,BUS->B
CUFSM <= S1;
WHEN S14=>
CTRL <= "100000000000100111111011"; --R0->BUS,BUS->B
CUFSM <= S1;
WHEN S15=>
IF INS = "00000000" THEN
CTRL <= "100000000000100111111011";
CUFSM <= S11;
ELSIF INS = "10000000" THEN
CTRL <= "100000000000000011111111";
CUFSM <= S27;
END IF;
WHEN S11=>
CTRL <= "100000000000100111111011"; --R0->BUS,BUS->B
CUFSM <= S1;
WHEN S27=>
CTRL <= "100000000000100111111011"; --R0->BUS,BUS->B
CUFSM <= S1;
END CASE;
END IF;
END PROCESS;

END CONTROLLER_ARCH ;

5、机器码验证程序：
$P 00 60 ; LDI R0,13H 将立即数13装入R0
$P 01 13
$P 02 30 ; OUT C0H,R0 将R0中的内容写入端口C0中，即写
$P 03 C0 ; ICW1，边沿触发，单片模式，需要ICW4
$P 04 60 ; LDI R0,30H 将立即数30装入R0
$P 05 30
$P 06 30 ; OUT C1H,R0 将R0中的内容写入端口C1中，即写
$P 07 C1 ; ICW2，中断向量为30-37
$P 08 60 ; LDI R0,03H 将立即数03装入R0
$P 09 03
$P 0A 30 ; OUT C1H,R0 将R0中的内容写入端口C1中，即写
$P 0B C1 ; ICW4，非缓冲，86模式，自动EOI
$P 0C 60 ; LDI R0,FEH 将立即数FE装入R0
$P 0D FE
$P 0E 30 ; OUT C1H,R0 将R0中的内容写入端口C1中，即写
$P 0F C1 ; OCW1，只允许IR0请求
$P 10 63 ; LDI SP,A0H 初始化堆栈指针为A0
$P 11 A0
$P 12 70 ; STI CPU开中断
$P 13 20 ; IN R0,00H 从端口00（IN单元）读入计数初值
$P 14 00
$P 15 41 ; LOOP：MOV R1,R0 移动数据，并等待中断
$P 16 E0 ; JMP LOOP 跳转，并等待中断
$P 17 15

; 以下为中断服务程序：
$P 20 80 ; CLI CPU关中断
$P 21 61 ; LDI R1,01H 将立即数01装入R1
$P 22 01
$P 23 04 ; ADD R0,R1 将R0和R1相加，即计数值加1
$P 24 30 ; OUT 40H,R0 将计数值输出到端口40（OUT单元）
$P 25 40
$P 26 70 ; STI CPU开中断
$P 27 B0 ; IRET 中断返回
$P 30 20 ; IR0的中断入口地址20

五、运行结果：

初始化8259，然后原地踏步等待中断，每中断一次R0 +1，把R0输出到OUT单元
计算了14次，如out 单元：

六、所遇问题及解决方法：
VHDL语言编程主要实现各个分支，这里要参照流程图，细心不出错后面实现就比较简单了。由于刚接触这种语言，开始犯了很多语法错误，后来在老师的帮助下逐一修改了过来。后面遇到最多的问题还是实验的接线，由于没有标准的接线图，又没有自己画出模拟图，导致接线错误频出，后来也在老师的帮助下改正了过来。

七、实验总结：
1.
本次实验由于内容较多，编程、设计也十分繁琐，导致小错不断，以后再做类似的工作时一定要画出流程图，一步一步细心完成；
2.
设计二进制代码时一定要注意0和1的位数，合理分配指令操作码；
3.
用visio绘制微程序流程图时要注意流程顺序。

八、建议：
1.
感觉实验时间很紧，觉得应适当延长课程设计时间，给同学们充分时间完成；
2.
可以考虑适当启用研究生当辅导老师，这样不仅可以减轻老师负担，还能便于管理和同学们的答疑；
3.
建议多联系课堂上所学过的知识，拓展知识面。

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