第六章电路参数及其提取.pptx

1 1Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu第一节第一节 信号传输延迟信号传输延迟数字电路的延迟由四部分组成：数字电路的延迟由四部分组成：v 门延迟门延迟v 连线延迟连线延迟v 扇出延迟扇出延迟v 大电容延迟大电容延迟2 2Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu由与输出节点相关的微分方程描述由与输出节点相关的微分方程描述近似处理近似处理简化的简化的RC充放电近似充放电近似tp=0.69 CL(Reqn+Reqp)/2ln(2)一、一、CMOS门延迟门延迟3 3Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu延迟和输入信号相关延迟和输入信号相关Low high变化变化两个输入同时变低两个输入同时变低tpLH 0.69 Rp/2 CL只有一个输入变低只有一个输入变低tpLH 0.69 Rp CLHigh low 变化变化两个输入同时变高两个输入同时变高tpLH 0.69 2Rn CLCLBRnARpBRpARnCintNAND 的延迟估计的延迟估计4 4Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu二、连线延迟二、连线延迟interwirefringepp5 5Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu描述引线描述引线RC延迟的模型可以分为集总模型（延迟的模型可以分为集总模型（lumped model）和分布）和分布模型（模型（distributed model）集总模型集总模型RC延迟延迟cwireDrivercapacitance per unit lengthVoutClumpedRDriverVout简单适于短引线简单适于短引线(r,c,L)VNVinrLVinVNrLrLrLrLcLcLcLcLcLr,c单位长度的引线电阻、电容单位长度的引线电阻、电容6 6Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu分布模型（分布模型（distributed model）RC延迟延迟节点节点i的电压所满足的方程的电压所满足的方程网络节点分得很密网络节点分得很密延迟时间与连线的长度的延迟时间与连线的长度的平方成正比！平方成正比！长连线加驱动器缓冲器长连线加驱动器缓冲器buffer反相器链反相器链7 7Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu门延迟和引线延迟一起考虑门延迟和引线延迟一起考虑RDriverVinVoutrw,cw,L门延迟和引线延迟的总延迟时间为门延迟和引线延迟的总延迟时间为t=0.69RDriverCw+(RwCw)/2 =RDriverCw+0.5rwcwL2 Rw=rwL,Cw=cwL长连线加驱动器缓冲器长连线加驱动器缓冲器buffer反相器链反相器链8 8Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuCLKPAD1500Cu500Cu1200Cu750CuCubuffer0buffer1buffer2buffer3buffer4CLK1CLK2CLK3CLK4三、电路扇出延迟三、电路扇出延迟 逻逻辑辑门门的的输输出出端端所所接接的的输输入入门门的的个个数数称称为为电电路的扇出：路的扇出：Fout。对于电路扇出参数的主要限制是：对于电路扇出参数的主要限制是：1010Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu 扇出端的负载等于每个输入端的栅电容之扇出端的负载等于每个输入端的栅电容之和：和：在在电电路路设设计计中中，如如果果一一个个反反相相器器的的扇扇出出为为N，即即Fout=N。其其驱驱动动能能力力应应提提高高N倍倍，才才能能获获得得与与其其驱驱动动一一级级门门相相同同的的延延迟迟时时间间。否则它的上升及下降时间都会下降否则它的上升及下降时间都会下降N倍。倍。1111Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu采用加入缓冲器使大扇入和大扇出相隔离采用加入缓冲器使大扇入和大扇出相隔离CLCL四、大电容负载驱动电路四、大电容负载驱动电路问问题题：一一个个门门驱驱动动非非常常大大的的负负载载时时，会会引引起起延延迟迟的的增增大大。由由于于外外部部电电容容比比芯芯片片内内部部标标准准门门栅栅电电容容可可能能要要大大几几个个数数量量级级。要要想想在在允允许许的的门门延延迟时间内驱动大电容负载，只有提高迟时间内驱动大电容负载，只有提高 即即增增大大W，将将使使栅栅面面积积L W增增大大，管管子子的的输输入入电电容容（即即栅栅电电容容）Cg也也随随之之增增大大，它它相相对对于于前前一一级级又又是是一一个个大大电电容容负负载载。问问题题并并没没有有解解决决？Mead和和Conway论论证证了了用用逐逐级级放放大大反反相相器器构构成成的驱动电路可有效地解决驱动大电容负载问题。的驱动电路可有效地解决驱动大电容负载问题。1313Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu设计关键：设计关键：驱动负载驱动负载CL需要多少级才能使延迟最小？需要多少级才能使延迟最小？每级反相器的尺寸如何确定？每级反相器的尺寸如何确定？M1414Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu驱动负载时反相器的延迟驱动负载时反相器的延迟Delay=Delay(本征）本征）Delay(负载）负载）设设Wp2Wn2W时上拉和下拉的电流相时上拉和下拉的电流相同，即有相同的上升和延迟时间同，即有相同的上升和延迟时间等价于等价于RC网络网络对于反相器链有：对于反相器链有：Cgin，j未知未知若反相器间保持固定的比例则若反相器间保持固定的比例则设每级间的尺寸比为设每级间的尺寸比为f，即每级有相同的延迟，即每级有相同的延迟对于给定的负载对于给定的负载CL和输入电容和输入电容Cin，可以确定其比例，可以确定其比例F，从而得到延，从而得到延迟最小条件下的优化尺寸迟最小条件下的优化尺寸忽略了反相器自身的负载，本征负载忽略了反相器自身的负载，本征负载Cint1717Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu1818Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu反相器链举例反相器链举例1919Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuLogical Effort 延迟模型延迟模型一般分析逻辑门的延迟是基于负载的，若要准确计算需一般分析逻辑门的延迟是基于负载的，若要准确计算需要精确的寄生参数和版图信息。但在逻辑设计和电路设要精确的寄生参数和版图信息。但在逻辑设计和电路设计阶段，无法得到这些信息，因此需要新的模型对延迟计阶段，无法得到这些信息，因此需要新的模型对延迟进行预算，而不必基于准确的寄生参数。进行预算，而不必基于准确的寄生参数。Logical Effort，LE通过比较不同逻辑结构的通过比较不同逻辑结构的延迟，评估延迟，评估CMOS电路的延迟电路的延迟2020Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu门延迟门延迟:gate delayd=h+peffort delayintrinsic delayEffort delay:h=g flogical efforteffective fanout =Cout/CinLogical effort 与电路拓扑结构相关，与器件的尺寸无关与电路拓扑结构相关，与器件的尺寸无关Effective fanout(electrical effort)是负载和器件尺寸的函数是负载和器件尺寸的函数逻辑门中的延迟逻辑门中的延迟门延迟的仔细区分门延迟的仔细区分依赖于负载和逻辑特性依赖于负载和逻辑特性依赖寄生特性依赖寄生特性2121Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuLogical Effort反相器的反相器的logical effort 和和 intrinsic delay 是所有静态是所有静态CMOS 门中最小的，取为门中最小的，取为1Logical effort 是该逻辑门和反相器在流过相同电流的是该逻辑门和反相器在流过相同电流的条件下逻辑门的输入电容与反相器的输入电容的比值，条件下逻辑门的输入电容与反相器的输入电容的比值，它独立于它独立于MOSFET的尺寸的尺寸逻辑门越复杂，逻辑门越复杂，Logical effort 越大越大Logical effort 是该逻辑门和反相器在流过相同电流的条件下逻辑门的是该逻辑门和反相器在流过相同电流的条件下逻辑门的输入电容与反相器的输入电容的比值输入电容与反相器的输入电容的比值g=1g=4/3g=5/3A+BABABABA BABAAA21Cunit=32222Cunit=44411Cunit=52323Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu各输入端的各输入端的LE可可能不一样能不一样ABC2424Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuLogical Effort2525Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu对于非标准逻辑门对于非标准逻辑门和非标准但和非标准但K相同的反相器比相同的反相器比等效反相器为等效反相器为2626Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuLogical Effort of GatesFan-out(h)Normalized delay(d)t1 23 4 5 6 7 pINVtpNANDF(Fan-in)g=1p=1d=h+1g=4/3p=2d=(4/3)h+22727Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liud=h+pg fp对于扇出为对于扇出为4的标准反相器的标准反相器g=1,f=4 若若g g0，p0,d=gf+p=4若若g g 1，p1,d=gf+p=5对于对于N级标准反相器构成的环振级标准反相器构成的环振g=1,f=1若若g g 0，p0,d1=gf+p=1DNd1N，freq1/2*N若若g g 1，p1,d1=gf+p=2DNd12*N，freq1/4*N2828Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuStage effort:hi=gifiPath electrical effort:F=Cout/CinPath logical effort:G=g1g2gNBranching effort:B=b1b2bNPath effort:H=GFBPath delay D=Sdi=Spi+ShiN级逻辑门相连级逻辑门相连2929Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuBranching effort:有分支的情况有分支的情况3030Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu优化设计优化设计当每一级具有相同当每一级具有相同effort delay时，为最优设计时，为最优设计:N级的最小延迟为级的最小延迟为每一级的等效扇出为每一级的等效扇出为:即即 Stage efforts:g1f1=g2f2=gNfN3131Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu对于给定的负载对于给定的负载CL和给定的第一级的输入电容和给定的第一级的输入电容Cin,可以证明最优的级数可以证明最优的级数N和级间比例为：和级间比例为：称为 best stage effort3232Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu计算出总的计算出总的:F=GBH估算出总级数估算出总级数 计算计算 stage effort f=F1/N按所需的级数实现逻辑功能按所需的级数实现逻辑功能逐级确定尺寸逐级确定尺寸:Cin=Cout*g/fReference:Sutherland,Sproull,Harris,“Logical Effort”,Morgan-Kaufmann 1999.优化设计方法优化设计方法3333Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu例：确定下列电路的尺寸，使延迟最小例：确定下列电路的尺寸，使延迟最小g=1f=ag=5/3f=b/ag=5/3f=c/bg=1f=5/cEffective fanout,F=5G=25/9H=FBG=125/9=13.9h=1.93H1/4a=1.93b=ha/g2=2.23c=hb/g3=5g4/f=2.59hgf1abcCL53434Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu3535Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu 第二节第二节 功功 耗耗 在功耗设计中主要考虑三个因素：在功耗设计中主要考虑三个因素：一一 导体的电迁移现象；导体的电迁移现象；二二 散热问题；散热问题；三三 供电问题。供电问题。3636Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuP6Pentium 486386286808680858080800840040.1110100197119741978198519922000YearPower(Watts)微处理器的功耗不断增加微处理器的功耗不断增加功耗及其散热将成为限制集成电路缩小的主要因素功耗及其散热将成为限制集成电路缩小的主要因素为什么需要考虑功耗为什么需要考虑功耗?芯片的功率密度芯片的功率密度40048008808080858086286386486PentiumP611010010001000019701980199020002010YearPower Density(W/cm2)Hot PlateNuclearReactorRocketNozzleSunsSurfacechips might become hot为什么需要考虑功耗为什么需要考虑功耗?电池的体积电池的体积/重量重量Expected battery lifetime increase over the next 5 years:30 to 40%From Rabaey,1995From Rabaey,199565 70 75 80 85 90 95 0 10 20 30 40 50 Rechargable LithiumYearNickel-CadmiumNi-Metal HydrideNominal Capacity(W-hr/lb)Battery(40+lbs)为什么需要考虑功耗为什么需要考虑功耗?待机功耗待机功耗 qDrain leakage will increase as VT decreases to maintain noise margins and meet frequency demands,leading to excessive battery draining standby power consumption.8KW 1.7KW 400W 88W 12W 0%10%20%30%40%50%20002002200420062008 Standby PowerSource:Borkar,De Intel Year20022005200820112014Power supply Vdd(V)1.51.20.90.70.6Threshold VT(V)0.40.40.350.30.25and phones leaky!4040Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu对于利用对于利用0.25 微米工艺制备的芯片，电源电压为微米工艺制备的芯片，电源电压为2.5V，500 MHz 的时钟频率下，平均负载电容为的时钟频率下，平均负载电容为15fF/gate，每，每门的平均扇出为门的平均扇出为4。假设每个时钟周期内状态翻转一次。假设每个时钟周期内状态翻转一次。请估算每级门的动态功耗。请估算每级门的动态功耗。若芯片上有若芯片上有108个门，则请估算整个芯片的动态功耗。个门，则请估算整个芯片的动态功耗。思考题思考题4141Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu一、金属线宽的确定一、金属线宽的确定 金属在传递电流时，电流密度有一定的限金属在传递电流时，电流密度有一定的限制。如果电流过大，而超过导体的域值制。如果电流过大，而超过导体的域值J Jthth，会使导体内产生电迁移现象，导致电路失，会使导体内产生电迁移现象，导致电路失效。效。AlAl的的J Jthth一般为一般为0.8-1.0 mA/m0.8-1.0 mA/m 例例如如：AlAl的的最最小小线线宽宽为为33，=2.5m=2.5m，AlAl的的厚厚度度约约为为1m1m，AlAl的的横横截截面面积积为为7.5m7.5m。4242Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu 取：取：Jth=1mA/mJth=1mA/m，则：导线可流过则：导线可流过7.5mA7.5mA的电流。如果电路实际工作电流大的电流。如果电路实际工作电流大于此电流值，就需要增加金属线宽，以于此电流值，就需要增加金属线宽，以防止电迁移现象出现。防止电迁移现象出现。4343Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu二、散热问题：二、散热问题：（1 1）减小各级门的功耗是集成电路设计目）减小各级门的功耗是集成电路设计目标之一。标之一。（2 2）降低功耗会使门的延迟时间增大。）降低功耗会使门的延迟时间增大。（3 3）目前，采用使散热均匀分布的方法来）目前，采用使散热均匀分布的方法来解决由于局部功耗过大，而造成的局部解决由于局部功耗过大，而造成的局部过热。过热。4444Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu三、供电问题：三、供电问题：在进行布线时，主要考虑的约束条件是：在进行布线时，主要考虑的约束条件是：（1 1）满足节点最大电压降的要求；满足节点最大电压降的要求；IRIR（2 2）满足电迁移的要求；满足电迁移的要求；（3 3）满足供电均匀的要求；满足供电均匀的要求；（4 4）满足噪声的要求。满足噪声的要求。优化目标是连线面积最小。优化目标是连线面积最小。