displayport interface.ppt

按一下以編輯母片標題樣式,按一下以編輯母片,第二層,第三層,第四層,第五層,*,Digital Display Interfaces,ATSZ-NB1,Elric_Jin,Digital Display Ports Enable and Disable Guidelines,NOTE:LVDS and eDP on processor can not be enabled at the same time.,Configuration Pin Mapping for DDI Ports,DisplayPort utilizes differential signaling to achieve a high-bandwidth bus interface to support both embedded chip-to-chip from processor and external box-to-box digital display connections from the PCH.A DisplayPort link consists of:Main link,Auxiliary Channel(AUX CH),Hot Plug Detect(HPD)signal:,DisplayPort,DisplayPort Main link utilizes a scrabbled 8b/10b encoding scheme for the data stream being transmitted.,If the bit rate is 2.7 Gb/s or 270 MB/s=(2.7 Gb/s x 1 Byte of data/10 b)is,supported,then four lanes would provide a peak bandwidth of,4 x 270 MB/s=1080 MB/s.,If the bit rate is 1.62 Gb/s,four lanes would provide a peak bandwidth of,4 x 162 MB/s=648 MB/s.,Main link,DisplayPort Main Link 4-Via External on Motherboard Topology,DisplayPort Main Link 4-Via External on Motherboard Routing Guidelines,DisplayPort Main Link 2-Via External on Motherboard Topology,DisplayPort Main Link 2-Via External on Motherboard Routing Guidelines,AUX CH consists of an AC-coupled,bi-directional differential-pair,providing a data rate of 1 Mbps.It is used for link management and device control,that is,for transmitting control and status information.,AUX CH is half-duplex and bi-directional.The source device is the master and Sink device is the slave.Manchester II coding is used as the channel coding for AUX CH.,Like the Main link the Aux Channel clock is embedded in the data stream.,AUX CH,DisplayPort Auxiliary Channel External Topology,DisplayPort Auxiliary Channel Routing Guidelines,DisplayPort HPD Passgate Design Recommendation,HPD,The Integrated High-Definition Multimedia Interface(HDMI)transmits digital television audiovisual signals from DVD players,set-top boxes and other audiovisual sources to television sets,projectors and other video displays.,HDMI is a display interface connecting the PCH and display devices that utilizes transition minimized differential signaling(TMDS)to carry audio-visual information through the same HDMI cable.,HDMI,HDMI includes three separate communications channels:TMDS,DDC,and the optional CEC(consumer electronics control).,Audio,video and auxiliary(control/status)data is transmitted across the three TMDS data channels.The video pixel clock is transmitted on the TMDS clock channel.,The maximum data rate supported for HDMI is 2.225 Gb/s.,Two level shifting options are supported-a Cost Reduced level shifter and an Activelevel shifter implementation.For designs supporting HDMI Deep Color at 2.225 Gb/s,it is highly recommended to use active level shifter optimized for 2.225 Gb/s.,HDMI Active Level shifter Motherboard Topology for Max Data Rate of 2.225Gb/s,Thank You!,