数字集成电路英文课件：Chapter 3-1Fabrication, Layout and Simulation.ppt

,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,*,单击此处编辑母版标题样式,*,Chapter 3:Fabrication,Layout and Simulation,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,2,Outline,CMOS,工艺流程,集成电路版图基础,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,3,主要的,CMOS,工艺,P,阱工艺,N,阱工艺,双阱工艺,P,-,P,+,P,+,N,+,N,+,P,+,N,+,V,SS,V,OUT,V,IN,V,DD,N,-,P,+,P,+,N,+,N,+,P,+,N,+,V,SS,V,OUT,V,IN,V,DD,P,-,P,+,P,+,N,+,N,+,P,+,N,+,V,SS,V,OUT,V,IN,N-Si,P-Si,N,-,I-Si,N,+,-Si,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,4,P,阱硅栅,CMOS,工艺,N,型衬底,p+,gate,oxide,p+,gate,oxide,oxide,N+,N+,P,阱,衬底选择：,确定衬底材料类型：,N,型硅,确定衬底材料电阻率：,10,.cm,确定衬底材料晶向,：（,100,）,晶向,（,111,）面的原子密度更大，所以更容易生长。生长成本最低，适合双极器件。,（,100,）面的表面状态有利于控制,MOS,器件开态和关态所需求的阈值电压。,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,5,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,6,掩膜,1,：,P,阱光刻,P-well,P-well,P,+,N,+,N,+,P,+,N-Si,P-well,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,7,制备,P,阱,Si(,固体,)+2H,2,O,SiO,2,（固体）,+2H,2,生长二氧化硅,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,8,P,阱光刻,涂胶,腌膜对准,曝光,光源,显影,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,9,P,阱掺杂,硼掺杂（离子注入）,刻蚀（等离子体刻蚀）,去胶,P+,去除氧化膜,P-well,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,10,掩膜,2:,光刻有源区,有源区：,nMOS,、,PMOS,晶体管形成的区域,P-well,P-well,淀积氮化硅,光刻有源区,场区氧化,去除有源区氮化硅及二氧化硅,SiO,2,隔离岛,P,+,N,+,N,+,P,+,N-Si,P-well,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,11,淀积氮化硅,P-well,氧化膜生长（湿法氧化）,P-well,氮化膜生长,P-well,涂胶,P-well,对版曝光,有源区光刻板,光刻有源区,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,12,场区氧化,P-well,显影,P-well,氮化硅刻蚀去胶,P-well,场区氧化（湿法氧化）,P-well,去除氮化硅薄膜及有源区,SiO,2,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,13,掩膜,3:,光刻多晶硅,P-well,去除氮化硅薄膜及有源区,SiO,2,P-well,栅极氧化膜,多晶硅栅极,生长栅极氧化膜,淀积多晶硅,光刻多晶硅,P,+,N,+,N,+,P,+,N-Si,P-well,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,14,P-well,生长栅极氧化膜,P-well,淀积多晶硅,P-well,涂胶光刻,多晶硅光刻板,P-well,多晶硅刻蚀,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,15,掩膜,4,：,P+,区光刻,P-well,P-well,P+,P+,P,+,N,+,N,+,P,+,N-Si,P-well,P+,区光刻,离子注入,B+,，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。,去胶,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,16,P-well,P+,P-well,P+,P+,硼离子注入,去胶,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,17,掩膜,5:N+,区光刻,P-well,P-well,P+,P+,N+,N+,P,+,N,+,N,+,P,+,N-Si,P-well,N+,区光刻,离子注入,P+,，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。,去胶,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,18,P-well,N+,P-well,P+,P+,磷离子注入,去胶,P+,P+,N+,N+,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,19,掩膜,6:,光刻引线孔,P-well,P-well,P+,P+,N+,N+,磷硅玻璃（,PSG),P,+,N,+,N,+,P,+,N-Si,P-well,淀积PSG,光刻接触孔,刻蚀接触孔,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,20,P-well,P+,P+,N+,N+,淀积,PSG,P-well,P+,P+,N+,N+,光刻接触孔,P-well,P+,P+,N+,N+,刻蚀接触孔,P-well,P+,P+,N+,N+,去胶,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,21,掩膜,7:,光刻铝线,P-well,P+,P+,N+,N+,P-well,淀积铝,光刻铝,去胶,P-well,P+,P+,N+,N+,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,22,掩膜,8:,刻压焊块,Circuit,PAD,CHIP,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,23,P,阱硅栅,CMOS,工艺掩膜板汇总,P,阱光刻,有源区光刻,多晶硅光刻,P+,区光刻,N+,区光刻,光刻引线孔,光刻铝线,刻压焊快,P,+,N,+,N,+,P,+,N-Si,P-well,P-well,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,24,双阱标准,CMOS,工艺,P+,p-epi,p well,n well,p+,n+,gate oxide,Al(Cu),tungsten,SiO,2,SiO,2,TiSi,2,field oxide,可分别对,NMOS,和,PMOS,器件进行设计与优化,两种器件之间的距离减小，增加器件密度,防止寄生晶体管效应（闩锁效应）,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,25,深亚微米,CMOS,晶体管结构,侧墙用来环绕多晶硅栅，防止大剂量源漏注入过于接近沟道以至可能发生的源漏击穿,LDD,防止热载流子效应等,轻掺杂区,浅槽隔离,侧墙,多晶硅硅化物,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,26,26,