模拟集成电路的分析与设计：Chapter 12-Switched-Capacitor circuits.ppt

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,Why switched-capacitor(1),First think about continuous-time feedback amplifier.,R,1,and R,2,affect the closed-loop gain;,Input resistance R,1,loads preceding stage.,Fig.12.1(a)Continuous feedback amplifier,(b)equivalent circuit,The transfer function can be calculated as,Why switched-capacitor(2),Using capacitor to replace the resistor and using R,F,to define the bias.,only if,(R,F,C,2,),-1,V,out,/V,in,-C,1,/C,2,for low frequency,the error is large.,High pass transfer function,Can use switched-capacitor in the amplifier to solve the problem!,switched-capacitor amplifier(1),Add switch S1,S2 and S3 into the amplifier.,Working at two phases:,sample phase,amplification phase,Fig.12.4 Switched-capacitor amplifier,switched-capacitor amplifier(2),At sample mode,switch S,1,and S,2,on,and S,3,off,the circuit can be refigured as:,For high gain op amps,Fig.12.5(a)Sampling mode,Voltage across C,1,approximately equal to V,in,and the charge stored on C1 is equal to V,in,C,1,switched-capacitor amplifier(3),At amplification mode,switch S,1,and S,2,off,and S,3,on,the circuit can be refigured as:,The charge stored on C1 at t=t0,Vin0C1,transferred to C2,Fig.12.5(b)Amplification mode,Fig.12.5(c),Fig.12.6 Transfer of charge from C,1,to C,2,Closed-loop op amp gain is C,1,/C,2,switched-capacitor amplifier(4),Use clock to control the switches and define the two phases:,MOSFETS as Switches(1),The switches can be performed by a single NMOS or PMOS,MOSFETS as Switches(2),The switches can also be performed by a transmission gate,MOSFETS as Switches(3),The needed complementary clocks can be generated by,Precision Consideration(1),A.Charge channel injection,When the channel is closed,half of the charge will be injected on to C,H,resulting a Vout error of,Precision Consideration(2),A.Charge channel injection cont.,Precision Consideration(3),A.Charge channel injection cont.,Charge injection will introduce the gain error,dc offsets,and non-linearity into the circuits.,Define a figure of Merit F=(,V),-1,Where,is the time constant and V is the error,A speed-precision trade-off exists!,Precision Consideration(4),B.Clock Feedthrough,Since there exists overlap capacitance,the clock transitions will introduce an error to the output,Same as charge injection,clock feedthrough will also lead to a speed-precision trade-off!,Precision Consideration(5),C.KT/C noise,The switch on resistance and the hold capacitance will produce thermal noise.When the switch off,the rms noise voltage of will be transferred to output,and leading to an error.,Increase C,H,can reduce the noise,but also slow down the circuits!,!,Charge injection and clock feedthrough cancellation(1),A.adding dummy device,If w,1,=2w,2,the charges injected by M,1,will be absorbed by M,2,and the clock feedthrough by M,1,and M,2,will be cancelled!,!,Charge injection and clock feedthrough cancellation(2),B.use of complementary switches,If the electrons injected equal to the holes injected,there will be no error at output,!,Charge injection and clock feedthrough cancellation(3),C.use of differential sampling circuit,If q,1,=q,2,the injection and feedthrough will be cancelled!,!,Switched-Capacitor amplifier(1),A.unity gain sampler/buffer,Switched-Capacitor amplifier(2),A.unity gain sampler/buffer cont.,Switches operation order:(1)s,1,and s,2,on,s,3,off,V,out,=0;,(2)s,2,off,then s,1,off,sample v,in,on C,H,;,(3)s,3,on,sampled v,in,amplified to v,out,.,Switched-Capacitor amplifier(3),A.unity gain sampler/buffer cont.,The clock generation circuit make sure s,2,first,then s,1,off,s,3,on last.,Switched-Capacitor amplifier(4),A.unity gain sampler/buffer-differential.,As mentioned before,the differential realization can cancel the charge injection and clock feedthrough.,The switch S,eq,turn off slightly after S2 and S2 off,but before S1 and S1 off.In this way,the circuit can cancel the charge injection mismatch produced by S2 and S2,Switched-Capacitor amplifier(5),A.unity gain sampler/buffer-precision consideration.,If the input capacitance of op amp is finite,the gain is not unity,there is a gain error!,Switched-Capacitor amplifier(6),A.unity gain sampler/buffer-speed consideration-sample mode.,Switched-Capacitor amplifier(7),A.unity gain sampler/buffer-speed consideration-amp mode.,Switched-Capacitor amplifier(8),B.non-inverting amplifier(1),Switched-Capacitor amplifier(9),B.non-inverting amplifier(2),If s,1,off after s,2,off,the charge injected by s,1,will not affect the output,the amplifier gain is C,1,/C,2,.,Switched-Capacitor amplifier(10),B.non-inverting amplifier(3),Switched-Capacitor amplifier(11),B.non-inverting amplifier(4),Switched-Capacitor amplifier(12),C.precision multiply-by-two circuit(1),Switches operation order:,s,1,s,2,and s,3,on,s,4,and s,5,off,circuit becomes as Fig.12.50(b),V,out,=0;,(2)s,3,off,then s,1,and s,2,off,s,4,and s,5,on,circuit becomes as Fig.12.50(c),v,out,=2v,in,.,Suppose C,1,=C,2,Switched-Capacitor amplifier(13),C.precision multiply-by-two circuit(2),When s5 on,left side of C2 connected to ground.Charges on C2(vin0)transferred to C1,so that Vout=2 Vin0,Switched-Capacitor amplifier(13),D.Switched-Capacitor Integrator,When s1 on s2 off,C1 sample the input voltage Vin;,When s1 off and s2 on,charges on C1(vin)transferred to C2,so that Vout increased by(C1/C2)Vin0.,The process is repeated,the integrator is obtained.,