VHDL十字路口交通灯.doc

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jiaotongdeng is
port( clk_in:in std_logic;
rst:in std_logic;
light:out std_logic_vector(7 downto 0);
zhug:out STD_LOGIC_VECTOR(6 downto 0);
zhus:out STD_LOGIC_VECTOR(6 downto 0);

zhig:out STD_LOGIC_VECTOR(6 downto 0);
zhis:out STD_LOGIC_VECTOR(6 downto 0));
end jiaotongdeng;

architecture a of jiaotongdeng is
type states is(green_red,yellow_red,red_green,red_yellow);
signal state:states:=green_red;
signal nextstate:states:=green_red;

signal dzhig:integer range 0 to 9;
signal dzhis:integer range 0 to 3;
signal dzhug:integer range 0 to 9;
signal dzhus:integer range 0 to 2;

signal clock_buffer:std_logic;
signal count_time:integer range 0 to 1999999;
signal clk:std_logic;

signal seczhig:integer range 0 to 9 ;
signal seczhis:integer range 0 to 3 ;
signal seczhug:integer range 0 to 9 ;
signal seczhus:integer range 0 to 2 ;
begin

frequent:process(clk_in)
begin
if clk_in'event and clk_in='1' then
if count_time=1999999 then
count_time<=0;
clock_buffer<=not clock_buffer;
else
count_time<=count_time+1;
end if;
end if;
clk<=clock_buffer;
end process;

light_statment:process(rst,state)
begin
if rst='0' then
light<="11011011";
NEXTSTATE<=YELLOW_RED;
else case state is
when green_red => light<="11011011";
nextstate<=yellow_red;
dzhus<=0;
dzhug<=4;
dzhis<=0
dzhig<=4;
when yellow_red => light<="10111011";
nextstate<=red_green;
dzhus<=2;
dzhug<=4;
dzhis<=1;
dzhig<=9;
when red_green =>light<="01111110";
nextstate<=red_yellow;
dzhus<=0;
dzhug<=4;
dzhis<=0;
dzhig<=4;
when red_yellow =>light<="01111101";
nextstate<=green_red;
dzhus<=2;
dzhug<=9;
dzhis<=3;
dzhig<=4;
end case;
end if;

end process;
time:process(rst,clk)
begin
if rst ='0'then
seczhus<=2;
seczhug<=9;
seczhis<=3;
seczhig<=4;
STATE<=GREEN_RED;
else
if (rising_edge(clk))then
if((seczhus=0 and seczhug=0 ) or (seczhis=0 and seczhig=0 ))then
state<=nextstate;
seczhus<=dzhus;
seczhug<=dzhug;
seczhis<=dzhis;
seczhig<=dzhig;

else
if((seczhus /= 0 and seczhug=0 ) and (seczhis /= 0 and seczhig=0 ))then
seczhus<=seczhus-1;
seczhug<=9;
seczhis<=seczhis-1;
seczhig<=9;

elsif(seczhis /= 0 and seczhig=0 ) then
seczhis<=seczhis-1;
seczhig<=9;
seczhug<=seczhug-1;
elsif(seczhus /= 0 and seczhug=0 ) then
seczhus<=seczhus-1;
seczhug<=9;
seczhig<=seczhig-1;

else
seczhug<=seczhug-1;
seczhig<=seczhig-1;
end if;

end if;
end if;
end if;
end process;
process(seczhus)

begin
case seczhus is
WHEN 0 => zhus <= "1000000" ;
WHEN 1 => zhus <= "1111001" ;
WHEN 2 => zhus <= "0100100" ;
WHEN others=>null;
END case;
END process;
process(seczhug)
begin
case seczhug is
WHEN 0 => zhug <= "1000000" ; --0
WHEN 1 => zhug<= "1111001" ; --1
WHEN 2 => zhug<= "0100100" ; --2
WHEN 3 => zhug<= "0110000" ; --3
WHEN 4 => zhug<= "0011001" ; --4
WHEN 5 => zhug<= "0010010" ; --5
WHEN 6 => zhug<= "0000010" ; --6
WHEN 7 => zhug<= "1111000" ; --7
WHEN 8 => zhug<= "0000000" ; --8
WHEN 9 => zhug<= "0010000" ; --9
END case;
END process;
process(seczhig)
begin
case seczhig is
WHEN 0 => zhig <= "1000000" ; --0
WHEN 1 => zhig <= "1111001" ; --1
WHEN 2 => zhig <= "0100100" ; --2
WHEN 3 => zhig <= "0110000" ; --3
WHEN 4 => zhig <= "0011001" ; --4
WHEN 5 => zhig <= "0010010" ; --5
WHEN 6 => zhig <= "0000010" ; --6
WHEN 7 => zhig <= "1111000" --7
WHEN 8 => zhig <= "0000000" ; --8
WHEN 9 => zhig <= "0010000" ; --9
END case;
END process;
process(seczhis)
begin
case seczhis is
WHEN 0 => zhis <= "1000000" ; --0
WHEN 1 => zhis <= "1111001" ; --1
WHEN 2 => zhis <= "0100100" ; --2
WHEN 3 => zhis <= "0110000" ; --3
END case;
END process;
end a;