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可编辑逻辑器件应用实验报告
浙江万里学院实验报告
成绩：
教师： 谢智波

课程名称：可编程逻辑器件应用
实验名称：频率计
专业班级：电子091 姓名： 潘益斌 学号： 2009017172
一． 实验题目：对输入信号测量显示频率
二．实验内容：
1.分频：50M分频，分别分频0.5hz和1hz代码如下
library ieee;
use ieee.std_logic_1164.all
entity div is
port(CLOCK_50:in std_logic;
bHz:out std_logic;
qkHz:out std_logic);
end div;
architecture hz of div is
constant fpb :integer :=99999999;
constant temp:integer :=49999999;
signal aqi :integer range 0 to fpb;

constant kfpb :integer :=49999;
constant ktemp:integer :=24999;
signal kaqi :integer range 0 to fpb;
begin
process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if aqi < fpb then
aqi <= aqi+1;
else
aqi <= 0;
end if;
end if;
end process;
process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if(aqi <= temp) then
bHz <= '1';
else
bHz <= '0';
end if;
end if;
end process;

process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if kaqi < kfpb then
kaqi <= kaqi+1;
else
kaqi <= 0;
end if;
end if;
end process;
process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if(kaqi <= ktemp) then
qkHz <= '1';
else
qkHz <= '0';
end if;
end if;
end process;

end;

2. 计数器：对高电平上升沿跳变次数进行计数程序代码如下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jishu is
port(en,clk:in std_logic;
data:out std_logic_vector(15 downto 0));
end jishu;

architecture aaa of jishu is
begin
process(en,clk)
variable num:std_logic_vector(15 downto 0);
begin
if en='0' then
num:="0000000000000000";
elsif en='1' then
if clk'event and clk='1' then
num:=num+'1';
data<=num;
end if;
end if;
end process;
end;
3转化10进制转化为二进制
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity encode is
port(bdata:in std_logic_vector(15 downto 0);
out1,out2,out3,out4,out5:out std_logic_vector(3 downto 0));
end encode;

architecture behave of encode is
begin
process(bdata)
variable tmp,q1,q2,q3,q4:integer;
begin
tmp:=conv_integer(bdata);
q1:=tmp/10;
q2:=q1/10;
q3:=q2/10;
q4:=q3/10;
out1<=conv_std_logic_vector(tmp rem 10,4);
out2<=conv_std_logic_vector(q1 rem 10,4);
out3<=conv_std_logic_vector(q2 rem 10,4);
out4<=conv_std_logic_vector(q3 rem 10,4);
out5<=conv_std_logic_vector(q4 rem 10,4);
end process;
end;
4锁存模块程序代码如下：
library ieee;
use ieee.std_logic_1164.all;
entity suocun is
port(clk:in std_logic;
data1,data2,data3,data4,data5:in std_logic_vector(3 downto 0);
out1,out2,out3,out4,out5:out std_logic_vector(3 downto 0)
);
end suocun;
architecture arch of suocun is
begin
process(clk)
begin
if clk'event and clk='0' then
out1<=data1;
out2<=data2;
out3<=data3;
out4<=data4;
out5<=data5;
end if;
end process;
end arch;
5译码显示：将数据显示在数码管上vhdl代码如下
library ieee;

use ieee.std_logic_1164.all;

entity xianshi is
port(jishu:in std_logic_vector(3 downto 0);
HEX0:out std_logic_vector(6 downto 0));
end xianshi ;

architecture decode of xianshi is
begin
with jishu select
HEX0 <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0011000" when "1001",
"ZZZZZZZ" when others;
end;
6内部频率产生模块内部27m分频产生内部2000hz频率
library ieee;
use ieee.std_logic_1164.all;

entity KDIV is
port(CLOCK_27:in std_logic;
ONEKHz:out std_logic);
end KDIV;

architecture hz of KDIV is
constant fpb :integer :=13499;
constant temp:integer :=6719;
signal aqi :integer range 0 to fpb;
begin
process(CLOCK_27)
begin
if rising_edge(CLOCK_27) then
if aqi < fpb then
aqi <= aqi+1;
else
aqi <= 0;
end if;
end if;
end process;
process(CLOCK_27)
begin
if rising_edge(CLOCK_27) then
if(aqi <= temp) then
ONEKHz <= '1';
else
ONEKHz <= '0';
end if;
end if;
end process;

end;
7通道选择 CH1 CH2区分内部和外部的频率来源
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choose is
port(sele,ch1,ch2:in std_logic;
hz:out std_logic);
end choose;

architecture behv of choose is
begin
with sele select
hz <= ch1 when '0',
ch2 when '1';
end;

电路图如下：

三． 实验现象及分析
实验中通过对频率信号的上升沿的次数进行计数并显示，因此板子上显示2000hz因为选用内部27m的晶振产生频率，当使用外部通道时，当一端接地ext-clock时候接入3170hz数码管后5段便显示3173hz
四．总结
在这次实验中使用分频译码和数码管显示频率计数在这次的实验中由于频率信号发生器只有一天因此使用内部27m的晶振分频得到1hz的频率，同时使用choose来选择是用内部的频率信号或者外部的信号，在这次实验中有很多模块都是以前使用的，所以在以后的使用中有许多的程序都可以保留这样一些用到的功能直接模块拖入便可以操作了。