触发器代码VHDL.doc

RS触发器
library ieee;
use ieee.std_logic_1164.all;
entity rsff is
port(r,s:in std_logic;
q,qb:out std_logic);
end rsff;
architecture rtl of rsff is
signal q_temp,qb_temp :std_logic;
begin
process(r,s)
begin
if(s='1'and r='0')then
q_temp<='0';
qb_temp<='1';
elsif(s='0'and r='1') then
q_temp<='1';
qb_temp<='0';
else
q_temp<=q_temp;
qb_temp<=qb_temp;
end if;
end process;
q<=q_temp;
qb<=qb_temp;
end rtl;

JK触发器
library ieee;
use ieee.std_logic_1164.all;
entity jk is
port(pset,clr,clk,j,k:in std_logic;
q,qb:out std_logic);
end entity jk;
architecture rt1 of jk is
signal q_s,qb_s:std_logic;
begin
process(pset,clr,clk,j,k)is
begin
if(pset='0')then
q_s<='1';
qb_s<='0';
elsif(clr='0')then
q_s<='0';
qb_s<='1';
elsif(clk'event and clk='1')then
if(j='0')and(k='1')then
q_s<='0';
qb_s<='1';
elsif(j='1')and (k='0')then
q_s<='1';
qb_s<='0';
elsif(j='1')and (k='1')then
q_s<=not q_s;
qb_s<=not qb_s;
end if;
end if;
q<=q_s;
qb<=qb_s;
end process;
end architecture;