数据采集模块及简易存储示波器设计.doc

RAM的VHDL设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY ram8 IS
PORT
(
address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
we : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram8;

ARCHITECTURE SYN OF ram8 IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);

COMPONENT lpm_ram_dq
GENERIC (
lpm_address_control : STRING;
lpm_indata : STRING;
lpm_outdata : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthad : NATURAL
);
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
we : IN STD_LOGIC
);
END COMPONENT;

BEGIN
q <= sub_wire0(7 DOWNTO 0);

lpm_ram_dq_component : lpm_ram_dq
GENERIC MAP (
lpm_address_control => "REGISTERED",
lpm_indata => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_type => "LPM_RAM_DQ",
lpm_width => 8,
lpm_widthad => 9
)
PORT MAP (
address => address,
inclock => inclock,
data => data,
we => we,
q => sub_wire0
);

END SYN;

计数器VHDL设计:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cont9b is
port (clk,lock0,rst,we:in std_logic;
dout:out std_logic_vector(8 downto 0);
clkout:out std_logic);
end cont9b;
architecture behave of cont9b is
signal cq1:std_logic_vector(8 downto 0);
signal clk0:std_logic;
begin
clk0<=lock0 when we='1' else
clk;
process(clk0,rst)
begin
if rst='1' then cq1<="000000000";
elsif rising_edge(clk0) then
cq1<=cq1+1;
end if;
end process;
dout<=cq1;
clkout<=clk0;
end;

ADC设计：
library ieee;
use ieee.std_logic_1164.all;
entity x_adc0809 is
port (d:in std_logic_vector(7 downto 0);
clk,rst:in std_logic;
eoc:in std_logic;
ale:out std_logic;
start,oe:out std_logic;
adda,lock_t:out std_logic;
q:out std_logic_vector(7 downto 0));
end entity x_adc0809;
architecture behave of x_adc0809 is
type states is (s0,s1,s2,s3,s4);
signal cs,next_state:states:=s0;
signal regl:std_logic_vector(7 downto 0);
signal lock:std_logic;
begin
adda<='0';lock_t<=lock;
com:process(cs,eoc)
begin
case cs is
when s0 => ale<='0';start<='0';oe<='0';lock<='0';next_state<=s1;
when s1 => ale<='1';start<='1';oe<='0';lock<='0';next_state<=s2;
when s2 => ale<='0';start<='0';oe<='0';lock<='0';
if(eoc='1') then next_state<=s3;
else next_state<=s2; end if;
when s3=>ale<='0';start<='0';oe<='1';lock<='0';next_state<=s4;
when s4=>ale<='0';start<='0';oe<='1';lock<='1';next_state<=s0;
when others=>ale<='0';start<='0';oe<='0';lock<='0';next_state<=s0;
end case;
end process com;
reg:process (clk,rst) begin
if rst='1' then cs<=s0;
elsif clk'event and clk='1' then cs<=next_state;
end if;
end process reg;
latch1:process (lock) begin
if lock='1' and lock'event then regl<=d;
end if;
end process latch1;
q<=regl;
end behave;

总体结构图设计：