四选一程序及仿真.doc

请用四种方法，描述数据选择器
输入端
输出端
a
b
out
0
0
in0
0
1
in1
1
0
in2
1
1
in3
in0
in3
in1
in2
a b b
out

方法1
module mux4_1(out,a,b,in);
input a,b;input [3:0]in;output out;
assign out =(!a&!b&in[0])| (!a&b&in[1])| (a&!b&in[2])| (a&b&in[3]);
endmodule

方法2
module mux4_1(out,a,b,in);
input a,b;input [3:0]in;output out;
wire na,nb,c1,c2,c3,c0;
not my_not1(na,a),my_not2(nb,b);
and my_and0(c0,na,nb,in[0]), my_and1(c1,na,b,in[1]), my_and2(c2,a,nb,in[2]), my_and3(c1,a,b,in[3]);
or my_or(out,c0,c1,c2,c3);
endmodule
方法3
module mux4_1(out,a,b,in);
input a,b;input [3:0]in;output reg out;
always@( a,b,in)begin
if(!a&&!b)out=in[0];
else if (!a&&b)out=in[1];
else if (a&&!b)out=in[2];
else out=in[3];
endmodule

方法4
module mux4_1(out,a,b,in);
input a,b;input [3:0]in;output reg out;
always@(a,b,in) begin
case({a,b})
0:out=in[0];
1:out=in[1];
2:out=in[2];
3:out=in[3];
default:out=1’bx;
endcase
end
endmodule

仿真程序
`timescale 1ns / 1ps
module mux4_1_tf;
reg a;
reg b;
reg [3:0] in=0;
wire out;
mux4_1 uut (
.out(out),
.a(a),
.b(b),
.in(in)
);
initial begin
a = 0;b = 0;#120;a = 0;b = 1;#150;
a = 1;b = 0;#160;a = 1;b = 1;#200;
end
always #30 in=in+1;
endmodule