MSP430寄存器详述.doc

/*********************************** 中断 ******************************/
/*中断使能1*/
#define IE1_ 0x0000
sfrb IE1 = IE1_;
#define WDTIE 0x01 /*看门狗中断使能*/
#define OFIE 0x02 /*外部晶振故障中断使能*/
#define NMIIE 0x10 /*非屏蔽中断使能*/
#define ACCVIE 0x20 /*可屏蔽中断使能/flash写中断错误*/
#define URXIE0 0x40 /*串口0接收中断使能*/
#define UTXIE0 0x80 /*串口0发送中断使能*/
中断使能IE1
UTXIE0
URXIE0
ACCVIE
NMIIE

OFIE
WDTIE
/*中断标志1*/
#define IFG1_ 0x0002
sfrb IFG1 = IFG1_;
#define WDTIFG 0x01 /*看门狗中断标志*/
#define OFIFG 0x02 /*外部晶振故障中断标志*/
#define NMIIFG 0x10 /*非屏蔽中断标志*/
#define URXIFG0 0x40 /*串口0接收中断标志*/
#define UTXIFG0 0x80 /*串口0发送中断标志*/
中断标志IFG1
UTXIFG0
URXIFG0

NMIIFG

OFIFG
WDTIFG
/* 中断模式使能1 */
#define ME1_ 0x0004
sfrb ME1 = ME1_;
#define URXE0 0x40 /* 串口0接收中断模式使能 */
#define USPIE0 0x40 /* 同步中断模式使能 */
#define UTXE0 0x80 /* 串口0发送中断模式使能 */
中断模式使能ME1
UTXE0
URXE0
USPIE0

/* 中断使能2 */
#define IE2_ 0x0001
sfrb IE2 = IE2_;
#define URXIE1 0x10 /* 串口1接收中断使能 */
#define UTXIE1 0x20 /* 串口1发送中断使能 */
中断使能IE2

UTXIE1
URXIE1

/* 中断标志2 */
#define IFG2_ 0x0003
sfrb IFG2 = IFG2_;
#define URXIFG1 0x10 /* 串口1接收中断标志 */
#define UTXIFG1 0x20 /* 串口1发送中断标志 */
中断标志IFG2

UTXIFG1
URXIFG1

/* 中断模式使能2 */
#define ME2_ 0x0005
sfrb ME2 = ME2_;
#define URXE1 0x10 /* 串口1接收中断模式使能 */
#define USPIE1 0x10 /* 同步中断模式使能 */
#define UTXE1 0x20 /* 串口1发送中断模式使能 */
中断模式使能ME2

UTXE1
URXE1
USPIE1

/********************************** 看门狗 ******************************/
#define WDTCTL_ 0x0120 P145
sfrw WDTCTL = WDTCTL_;
#define WDTIS0 0x0001 /*选择WDTCNT的四个输出端之一*/
#define WDTIS1 0x0002 /*选择WDTCNT的四个输出端之一*/
#define WDTSSEL 0x0004 /*选择WDTCNT的时钟源*/
#define WDTCNTCL 0x0008 /*清除WDTCNT端: 为1时从0开始计数*/
#define WDTTMSEL 0x0010 /*选择模式 0: 看门狗模式; 1: 定时器模式*/
#define WDTNMI 0x0020 /*选择NMI/RST 引脚功能 0:为 RST; 1:为NMI*/
#define WDTNMIES 0x0040 /*WDTNMI=1时.选择触发延 0:为上升延 1:为下降延*/
#define WDTHOLD 0x0080 /*停止看门狗定时器工作 0:启动;1:停止*/
看门狗控制寄存器WDTCTL
口令
WDTHOLD
WDTNMIES
WDTNMI
WDTTMSEL
WDTCNTCL
WDTSSEL
WDTIS1
WDTIS0
注：口令（15-8）：读取为69H，写为5AH。
#define WDTPW 0x5A00 /* 写密码:高八位*/

/* SMCLK= 1MHz定时器模式 */
#define WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL
/* TSMCLK*2POWER15=32ms 复位状态 */
#define WDT_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0
/* TSMCLK*2POWER13=8.192ms */
#define WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1
/* TSMCLK*2POWER9=0.512ms */
#define WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0
/* TSMCLK*2POWER6=0.512ms */

/* ACLK=32.768KHz 定时器模式*/
#define WDT_ADLY_1000 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL
/* TACLK*2POWER15=1000ms */
#define WDT_ADLY_250 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0
/* TACLK*2POWER13=250ms */
#define WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1
/* TACLK*2POWER9=16ms */
#define WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0
/* TACLK*2POWER6=1.9ms */

/* SMCLK=1MHz看门狗模式 */
#define WDT_MRST_32 WDTPW+WDTCNTCL
/* TSMCLK*2POWER15=32ms 复位状态 */
#define WDT_MRST_8 WDTPW+WDTCNTCL+WDTIS0
/* TSMCLK*2POWER13=8.192ms */
#define WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1
/* TSMCLK*2POWER9=0.512ms */
#define WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTIS0
/* TSMCLK*2POWER6=0.512ms */

/* ACLK=32.768KHz看门狗模式 */
#define WDT_ARST_1000 WDTPW+WDTCNTCL+WDTSSEL
/* TACLK*2POWER15=1000ms */
#define WDT_ARST_250 WDTPW+WDTCNTCL+WDTSSEL+WDTIS0
/* TACLK*2POWER13=250ms */
#define WDT_ARST_16 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1
/* TACLK*2POWER9=16ms */
#define WDT_ARST_1_9 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0
/* TACLK*2POWER6=1.9ms */

/****************************** 基本定时器 ***************************/
#define BTCTL_ (0x0040) /* 控制寄存器 */
MSP430F4XX系列(P148)
#define BTIP0 (0x01)
#define BTIP1 (0x02)
#define BTIP2 (0x04) /*BTIP2-0：定时中断频率*/
#define BTFRFQ0 (0x08)
#define BTFRFQ1 (0x10) /*输出fLCD信号*/
#define BTDIV (0x20) /* fCLK2 = ACLK:256 */
#define BTHOLD (0x40) /* 0:启动;1:停止*/
#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */
基本计时器控制寄存器
BTSSEL
BTHOLD
BTDIV
BTFRFQ1
BTFRFQ0
BTIP2
BTIP1
BTIP0

#define BTCNT1_ (0x0046) /* Basic Timer Count 1 */

#define BTCNT2_ (0x0047) /* Basic Timer Count 2 */

/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
#define BT_fCLK2_ACLK (0x00)
#define BT_fCLK2_ACLK_DIV256 (BTDIV) /*256分频*/
#define BT_fCLK2_MCLK (BTSSEL)
#define BT_fCLK2_ACLK_DIV256 (BTSSEL+BTDIV) /*很少使用吧*/

/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */

/* Frequency of LCD coded with Bits 3-4 */
#define BT_fLCD_DIV32 (0x00) /* fLCD = fACLK:32 (default) */
#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD = fACLK:64 */
#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD = fACLK:128 */
#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) /* fLCD = fACLK:256 */
/* LCD frequency values with fBT=fACLK */
#define BT_fLCD_1K (0x00) /* fACLK:32 (default) */
#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */
#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */
#define BT_fLCD_128 (BTFRFQ1+BTFRFQ0) /* fACLK:256 */
/* LCD frequency values with fBT=fMCLK */
#define BT_fLCD_31K (BTSSEL) /* fMCLK:32还是fMCLK？*/
#define BT_fLCD_15_5K (BTSSEL+BTFRFQ0) /* fMCLK:64 */
#define BT_fLCD_7_8K (BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 */
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
/* fBT=fACLK is thought for longer interval times */

#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
#define BT_ADLY_1 (BTIP2) /* 1ms " */
#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
#define BT_ADLY_16 (BTDIV) /* 16ms " */
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
/* the timing for short intervals is more precise than ACLK */

/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
/* Too low interval time results in interrupts too frequent for the processor to handle! */
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms *** too short for */
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms *** interrupt */
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms *** handling */
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */

/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
/* this is for BT */
//#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set */
//#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
/* this is for BT1 */
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */

/* INTERRUPT CONTROL BITS */
/* #define BTIE 0x80 */
/* #define BTIFG 0x80 */
/******************************* 定时器 A3 *****************************/
#define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV , TAIV_)
#define TACTL_ (0x0160) /* Timer A Control */
DEFW( TACTL , TACTL_)
#define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */
DEFW( TACCTL0 , TACCTL0_)
#define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */
DEFW( TACCTL1 , TACCTL1_)
#define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */
DEFW( TACCTL2 , TACCTL2_)
#define TAR_ (0x0170) /* Timer A */
DEFW( TAR , TAR_)
#define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */
DEFW( TACCR0 , TACCR0_)
#define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */
DEFW( TACCR1 , TACCR1_)
#define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */
DEFW( TACCR2 , TACCR2_)

/* Alternate register names */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */

/*TACTL:定时器A控制寄存器↓*/
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
#define ID1 (0x0080) /* Timer A clock input divider 1 */
#define ID0 (0x0040) /* Timer A clock input divider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
15-10
9
8
7
6
5
4
3
2
1
0
X
TASSEL1
TASSEL0
ID1
ID0
MC1
MC0
X
TACLR
TAIE
TAIFG
/*MC1.MC0:计数模式控制位*/
#define MC_0 (0*0x10u) /* 00停止模式 */
#define MC_1 (1*0x10u) /* 01增计数模式 */
#define MC_2 (2*0x10u) /* 10连续计数模式 */
#define MC_3 (3*0x10u) /* 11增减计数模式 */
/*ID1.ID0:输入分频选择*/
#define ID_0 (0*0x40u) /* 00：不分频 */
#define ID_1 (1*0x40u) /* 01：2分频 */
#define ID_2 (2*0x40u) /* 10：4分频 */
#define ID_3 (3*0x40u) /* 11：8分频 */
/*SSEL1.SSEL0:输入分频器的时钟源选择*/
#define TASSEL_0 (0*0x100u) /* 00：TACLK见具体器件说明 */
#define TASSEL_1 (1*0x100u) /* 01：ACLK */
#define TASSEL_2 (2*0x100u) /* 10：SMCLK */
#define TASSEL_3 (3*0x100u) /* 11：INCLK见具体器件说明 */

/*TACCTLx:捕获/比较控制寄存器↓*/
#define CM1 (0x8000) /* Capture mode 1 */
#define CM0 (0x4000) /* Capture mode 0 */
#define CCIS1 (0x2000) /* Capture input select 1 */
#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* 0：异步捕获；1：同步捕获 */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* 0：比较模式；1：捕获模式 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* 0：禁止中断；1：允许中断*/
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* 捕获溢出标志（1为溢出） */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
15.14
13.12
11
10
9
8
7.6.5
4
3
2
1
0
CM1.0
CCIS1.0
SCS
SCCI

CAP
OUTMOD2.1.0
CCIE
CCI
OUT
COV
CCIFG
/*OUTMODx:输出模式选择 */
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 – 输出 */
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 – 置