北理工VHDL实验报告.doc

本科实验报告实验名称： VHDL语言及集成电路设计实验 课程名称：VHDL语言及集成电路设计实验时间：2014.5任课教师：桂小琰实验地点：4-427实验教师：任仕伟实验类型： 原理验证 综合设计 自主创新学生姓名：学号/班级：组 号：学 院：信息与电子学院同组搭档：专 业：电子科学与技术成 绩：实验一：带有异步复位端的D触发器一、实验目的（1）熟悉linux操作环境和modelsim软件环境（2）理解时序逻辑和组合逻辑电路的区别（3）理解并行语句和顺序语句（4）用VHDL语言编写一个带有异步复位端的D触发器及其测试文件二、实验原理（1）组合逻辑和时序逻辑组合逻辑电路当前输出的值仅取决于当前的输入，不需要触发器等具有存储能力的逻辑单元，仅仅使用组合逻辑门时序逻辑电路的当前输出不仅取决于当前的输入，还与以前的输入有关，这类电路中包括寄存器等元件，也包括组合逻辑电路，寄存器通过一个反馈环和组合逻辑模块相连。触发器便是属于时序逻辑电路（2）并行和顺序代码从本质上讲，VHDL代码是并发执行的。只有PROCESS，FUNCTION或PROCEDURE内的代码才是顺序执行的。当它们作为一个整体时，与其他模块之间又是并发执行的。以下是3个并发描述语句（stat1,stat2和stat3）的代码，会产生同样的电路结构。stat1 stat3 stat1stat2 = stat2 = stat3 = 其他排列顺序stat3 stat1 stat2（3）并行语句进程（PROCESS） 语法结构：进程名: PROCESS (敏感信号列表)变量说明语句BEGIN(顺序执行的代码)END PROCESS 进程名； PROCESS 的特点1多进程之间是并行执行的；2进程结构内部的所有语句都是顺序执行的；3进程中可访问结构体或实体中所定义的信号；4进程的启动是由敏感信号列表所标明的信号来触发，也可以用WAIT语句等待一个触发条件的成立。5各进程之间的通信是由信号来传递的。（4）带有异步复位端的D触发器 电路符号 功能表RDCPQ0xx01x0保持1x1保持10上升沿011上升沿1三、实验代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dff ISPORT(d,clk,rst:IN STD_LOGIC; q:OUT STD_LOGIC);END dff; ARCHITECTURE behavior OF dff IS BEGIN PROCESS(rst,clk) BEGIN IF(rst=1) THEN q=0; ELSIF(clkEVENT AND clk=1) THEN qd,clk=clk,rst=rst,q=q); clk_gen:process begin clk=0; wait for clk_period/2; clk=1; wait for clk_period/2; end process; d_gen:process begin wait for 100 ns; d=1; wait for 100 ns; d=0; end process; rst_gen:process begin rst=1; wait for 150 ns; rst=0; wait for 500 ns; rst=1; wait for 150 ns; wait; end process;end tb_behavior;四、仿真结果实验二 步进电机控制器一、实验目的（1）理解两种状态机的区别（2）熟悉两种编程风格（3）编写BCD计数器和步进电机二、实验原理（1）米里型状态机和摩尔型状态机米里（Mealy）型状态机:状态机的输出信号不仅与电路的当前状态有关，还与当前的输入有关摩尔（Moore）型状态机：状态机的当前输出仅仅由当前状态决定（2）有限状态机设计流程：1 理解问题背景。2 逻辑抽象，得出状态转移图。3 状态简化。4 状态分配。5 用VHDL来描述有限状态机。（3）BCD计数器原理图（4）步进电机控制器原理图步进电机状态与输出信号的对应关系状态输出状态S0S1S2S30001001001001000三、实验代码（1）BCD计数器library ieee;use ieee.std_logic_1164.all;entity counter is port(clk,rst:in std_logic;count:out std_logic_vector(3 downto 0);end counter;architecture state_machine of counter istype state is(zero,one,two,three,four,five,six,seven,eight,nine);signal pr_state,nx_state:state;begin process (rst,clk) begin if(rst=1)then pr_state count =0000; nx_state count =0001; nx_state count =0010; nx_state count =0011; nx_state count =0100; nx_state count =0101; nx_state count =0110; nx_state count =0111; nx_state count =1000; nx_state count =1001; nx_state = zero; end case; end process; end state_machine; （2）步进电机控制器library ieee;use ieee.std_logic_1164.all;entity stepmotor is port(clk,rst,x:in std_logic;output:out std_logic_vector(3 downto 0);end stepmotor;architecture state_machine of stepmotor istype state is(s0,s1,s2,s3);signal pr_state,nx_state:state;begin process (clk,rst) begin if(rst=1)then pr_state=s0; elsif(clk event and clk =1)then pr_state output =0001; nx_state output =0010; nx_state output =0100; nx_state output =1000; nx_state output =0001; nx_state output =0010; nx_state output =0100; nx_state output =1000; nx_state = s0; end case; end if; end process; end state_machine;四、仿真结果BCD计数器步进电机控制器实验三 十六位加法器设计一、实验目的（1）掌握元件例化的方法（2）理解for/generate语句的用法（3）编程完成4位加法器和16位加法器的设计二、实验原理（1）元件的例化元件声明是对VHDL模块（即底层设计，也是完整的VHDL设计）的说明，使之可在其他被调用，元件声明可放在程序包中，也可在某个设计的构造体中声明。元件例化指元件的调用。元件声明及元件例化的语法分别如下：元件声明：component元件实体名prot（元件端口信息，同该元件实现时的实体的port部分）；endcompnent；元件例化：例化名：实体名，即元件名portmap（端口列表）；（2）生成语句（GENERATE）GENERATE语句用于循环执行某项操作。FOR模式的生成语句主要用于相同结构的描述中；FOR模式语法结构：FOR/GENERATE:标号：FOR 变量IN 离散区间GENERATE（并行处理语句）；END GENERATE；（3）16位加法器的设计三、实验代码4位加法器：library ieee;use ieee.std_logic_1164.all;entity adder4 is port(a,b:in std_logic_vector(3 downto 0); cin:in std_logic; s:out std_logic_vector(3 downto 0); cout:out std_logic);end adder4;architecture behav of adder4 issignal c: std_logic_vector(4 downto 0);signal p: std_logic_vector(3 downto 0);signal g: std_logic_vector(3 downto 0);begin G1:for i in 0 to 3 generate p(i)=a(i) xor b(i); g(i)=a(i) and b(i); s(i)=p(i) xor c(i);end generate;c(0)=cin;c(1)=(cin and p(0) or g(0);c(2)=(cin and p(0) and P(1) or (g(0) and p(1) or g(1);c(3)=(cin and p(0) and P(1)and P(2) or (g(0) and p(1) and P(2) or (g(1) and P(2) or g(2);c(4)=(cin and p(0) and P(1)and P(2) and P(3) or (g(0) and p(1) and P(2) and P(3) or (g(1) and P(2) and P(3) or (g(2) and P(3) or g(3);couta,b=b,s=s,cin=cin,cout=cout ); processbegin a=x0000; b=x0000; cin=1; wait for 100ns; a=0000100000000001; b=0100000000000111; cin=0; wait for 100ns; a=x1111; b=x1111; cin=1; wait for 100ns; a=0000100000000001; b=1110000000000111; cin=1; wait ; end process;end behav;四、仿真结果实验四 选择运算器一、实验目的：（1）对前几次实验用到的知识进行总结（2）综合运用理论课上的知识，完成选择运算器的设计二、实验原理（1）设计要求：输出信号：一个COUT（15:0） ，16位乘法器：要求用部分积实现加法器：8位加法器，高7位补零完成比较器、乘法器、加法器的设计，不可以直接使用+，x运算符直接实现。（2）选择器运算器总原理图如下：（3）乘法器部分采用并行乘法器（4）加法器：8位加法器的设计和上一个试验类似，先设计一个4位加法器，进而编译8位加法器。三、实验代码与门：library ieee;use ieee.std_logic_1164.all;entity and_2 is port(a,b:in std_logic; y:out std_logic);end and_2;architecture behav of and_2 isbegin y= a and b;end behav; 全加器：library ieee;use ieee.std_logic_1164.all;entity fau is port(a,b,cin:in std_logic; s,cout:out std_logic);end fau;architecture behav of fau isbegin s=a xor b xor cin; cout=(a and b)or(a and cin)or(b and cin); end behav;顶层：library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity top_row is port(a:in std_logic; b:in std_logic_vector(7 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end top_row;architecture behav of top_row isbegin u1:component and_2 port map(a,b(7),sout(6); u2:component and_2 port map(a,b(6),sout(5); u3:component and_2 port map(a,b(5),sout(4); u4:component and_2 port map(a,b(4),sout(3); u5:component and_2 port map(a,b(3),sout(2); u6:component and_2 port map(a,b(2),sout(1); u7:component and_2 port map(a,b(1),sout(0); u8:component and_2 port map(a,b(0),p); u9:for i in 0 to 6 generate cout(i)=0; end generate;end behav;中层：library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity mid_row is port(a:in std_logic; b:in std_logic_vector(7 downto 0); sin,cin:in std_logic_vector(6 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end mid_row;architecture behav of mid_row issignal and_out:std_logic_vector(6 downto 0);begin u1:component and_2 port map(a,b(7),sout(6); u2:component and_2 port map(a,b(6),and_out(6); u3:component and_2 port map(a,b(5),and_out(5); u4:component and_2 port map(a,b(4),and_out(4); u5:component and_2 port map(a,b(3),and_out(3); u6:component and_2 port map(a,b(2),and_out(2); u7:component and_2 port map(a,b(1),and_out(1); u8:component and_2 port map(a,b(0),and_out(0); u9:component fau port map(sin(6),cin(6),and_out(6),sout(5),cout(6); u10:component fau port map(sin(5),cin(5),and_out(5),sout(4),cout(5); u11:component fau port map(sin(4),cin(4),and_out(4),sout(3),cout(4); u12:component fau port map(sin(3),cin(3),and_out(3),sout(2),cout(3); u13:component fau port map(sin(2),cin(2),and_out(2),sout(1),cout(2); u14:component fau port map(sin(1),cin(1),and_out(1),sout(0),cout(1); u15:component fau port map(sin(0),cin(0),and_out(0),p,cout(0); end behav;底层：library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity lower_row is port(sin,cin:in std_logic_vector(6 downto 0); p:out std_logic_vector(7 downto 0);end lower_row;architecture behav of lower_row is signal local:std_logic_vector(6 downto 0);beginlocal(0)=0;u1:component fau port map(sin(0),cin(0),local(0),p(0),local(1); u2:component fau port map(sin(1),cin(1),local(1),p(1),local(2); u3:component fau port map(sin(2),cin(2),local(2),p(2),local(3); u4:component fau port map(sin(3),cin(3),local(3),p(3),local(4);u5:component fau port map(sin(4),cin(4),local(4),p(4),local(5); u6:component fau port map(sin(5),cin(5),local(5),p(5),local(6); u7:component fau port map(sin(6),cin(6),local(6),p(6),p(7); end behav;乘法器用到的的元件声明：library ieee;use ieee.std_logic_1164.all;package my_components is component and_2 is port(a,b:in std_logic; y:out std_logic); end component; component fau is port(a,b,cin:in std_logic; s,cout:out std_logic); end component; component top_row is port(a:in std_logic; b:in std_logic_vector(7 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end component; component mid_row is port(a:in std_logic; b:in std_logic_vector(7 downto 0); sin,cin:in std_logic_vector(6 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end component; component lower_row is port(sin,cin:in std_logic_vector(6 downto 0); p:out std_logic_vector(7 downto 0); end component; end my_components;乘法器：library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity multiplier is port(a,b:in std_logic_vector(7 downto 0); prod:out std_logic_vector(15 downto 0);end multiplier;architecture behav of multiplier istype matrix is array (0 to 7) of std_logic_vector(6 downto 0);signal s,c:matrix;beginu1:component top_row port map(a(0),b,s(0),c(0),prod(0);u2:component mid_row port map(a(1),b,s(0),c(0),s(1),c(1),prod(1);u3:component mid_row port map(a(2),b,s(1),c(1),s(2),c(2),prod(2);u4:component mid_row port map(a(3),b,s(2),c(2),s(3),c(3),prod(3);u5:component mid_row port map(a(4),b,s(3),c(3),s(4),c(4),prod(4);u6:component mid_row port map(a(5),b,s(4),c(4),s(5),c(5),prod(5);u7:component mid_row port map(a(6),b,s(5),c(5),s(6),c(6),prod(6);u8:component mid_row port map(a(7),b,s(6),c(6),s(7),c(7),prod(7);u9:component lower_row port map(s(7),c(7),prod(15 downto 8);end behav;4位加法器：library ieee;use ieee.std_logic_1164.all;entity adder4 is port(a,b:in std_logic_vector(3 downto 0); cin:in std_logic; s:out std_logic_vector(3 downto 0); cout:out std_logic);end adder4;architecture behav of adder4 issignal c: std_logic_vector(4 downto 0);signal p: std_logic_vector(3 downto 0);signal g: std_logic_vector(3 downto 0);begin G1:for i in 0 to 3 generate p(i)=a(i) xor b(i); g(i)=a(i) and b(i); s(i)=p(i) xor c(i);end generate;c(0)=cin;c(1)=(cin and p(0) or g(0);c(2)=(cin and p(0) and P(1) or (g(0) and p(1) or g(1);c(3)=(cin and p(0) and P(1)and P(2) or (g(0) and p(1) and P(2) or (g(1) and P(2) or g(2);c(4)=(cin and p(0) and P(1)and P(2) and P(3) or (g(0) and p(1) and P(2) and P(3) or (g(1) and P(2) and P(3) or (g(2) and P(3) or g(3);cout=c(4);end behav;8位加法器：library ieee;use ieee.std_logic_1164.all;entity adder is port(a,b:in std_logic_vector(7 downto 0);