射频电路设计技巧及其电磁相容性.pptx

Lecture 2Richard Li,20111 第第1课课射频电路和数字电路设计上的差异射频电路和数字电路设计上的差异1.射频电路和数字电路在通信系统中的差异射频电路和数字电路在通信系统中的差异 o 阻抗 o 电流 o 位置 o 主要参数 o 主要功能2.信号源到负载的电压传输信号源到负载的电压传输 o 电压传输的一般公式 o 数字电路中额外的失真和抖动 3.信号源到负载的功率传输信号源到负载的功率传输 o 功率传输的一般公式 o 功率不稳定性 o 额外功率损失 o 额外失真 o 额外干扰4.阻抗共轭匹配阻抗共轭匹配 o 最大功率传输 o 无相移的功率传输 o 阻抗匹配网络5.阻抗匹配的重要意义阻抗匹配的重要意义o 功率测量 o 通过阻抗匹配上拉电压 o 晶体管击穿Problems Lecture 2Richard Li,201121.数字电路和数字电路和RF电路在通信系统中的差异电路在通信系统中的差异 o 阻抗 o 电流 o 位置 o 主要参数 o 主要功能o情形情形1低速数字电路低速数字电路Table1RF电路与低速数字电路的差异电路与低速数字电路的差异whereR=数据速率数据速率,fRF=RF频率（频率（MHz到到GHz）ItemItemRFRF电路电路数字电路数字电路ImpedanceImpedanceLow(50 Low(50 typically)typically)HighHighCurrentCurrentHigh(High(mAmA)Low (Low (AA)在无线通信系统中的在无线通信系统中的位置位置RxRxFront end(Front end(解调器之前解调器之前)Back end(Back end(解调器之后解调器之后)TxTxBack end(Back end(调制器之后调制器之后)Front end(Front end(调制器之前调制器之前)Transportation typeTransportation typePower(Power(WattWatt)Status(Voltage or current)Status(Voltage or current)Impedance matchingImpedance matchingImportantImportantDonDont care(usually)t care(usually)Lecture 2Richard Li,20113首先，阻抗完全不同。RF 电路的输入输出阻抗一般情况下是相当低的，大部分射频设备的典型阻抗是50。而数字电路的输入输出阻抗一般都很高，例如Op-amp（运算放大器）的输入和输出阻抗一般都高于10k。P=V2/Z 对于给定的功率，V2正比于Z。也就是说，模块的阻抗越高，则模块上的压降越大，反之，阻抗降低时，模块的压降也降低。不管是从电路的成本还是工程设计来看，低电压的应用优于高电压。这就是为什么RF模块的输入输出阻抗故意设置得很低，阻抗越低，只需要较低的电压就能建立相同的功率。然而，数字信号与此相反，数字信号要求传输状态。对于给定的电流，高阻抗可以在模块上建立高的电压摆幅，信号可以更有效的对器件进行开/关操作。因此，一个高阻抗模块只要很低的电流就可以产生足够的电压摆幅。第二，在射频电路设计中，不管是输入阻抗还是输出阻抗，必须要考虑阻抗匹配，这非常重要。也就是说，输入阻抗必须与信号源的阻抗匹配，输出阻抗必须与负载的阻抗匹配。阻抗匹配是判断RF 电路设计是否正确的一个重要的标准。然而在数字电路中，较少考虑阻抗匹配。Lecture 2Richard Li,20114oComparisonRF blocks:Foragivenvoltagev,LowZ HighHighi Itisbeneficialtothepowertransportationormanipulation!Digitalblocks:Foragivencurrenti,HighZ High LowP Itisbeneficialtothestatustransportationormanipulation!Lecture 2Richard Li,20115第三，RF 电路模块中的电流一般在毫安级，而数字电路模块的电流在微安级，它们相差1000 倍。前面提过，射频电路和数字电路的主要差别在于射频电路需要做阻抗匹配。而阻抗匹配的目的是实现功率的最大传输。也就是说，RF 电路的主要功能是功率传送。在RF 电路模块中，低阻抗和高吸入电流有利于功率传输，因此是必须的。相反，低速数字电路不需要阻抗匹配，因为它不需要传输功率。我们关心的是数字电路如何传输状态“0”和“1”，即数字电路传输的是数字信号的状态而不是数字信号的功率。在“0”和“1”可以得到传输的情况下，尽量减少数字信号的功率。低速数字电路应首选低电流和高阻抗，这样有利于节省功耗。总之，低速数字电路是传输和处理状态，RF 电路是传输和处理功率，因此数字电路设计和RF 电路设计的任务不同，特点也不同。Lecture 2Richard Li,20116为什么RF 信号是功率传输而数字信号是状态传输？在实际电路设计中这样的要求能否对调？答案可以从RF电路和数字电路在无线通信系统中的位置来寻找。RF 模块和数字模块之间是调制和解调器。在传输模块中，数字信号被调制成载波，只要求在调制模块前达到有效调制状态。这表明输入到调制器的数字信号不管是功率还是电压都可以很低，只要能够有效地调制载波即可。在这种情形下，数字信号在本地模块间传输和处理，不需要功率传输。然而调制后的载波必须进行功率放大并且从天线发射出去。因此调制后的载波应有足够的功率，以传播很长的距离，让远处的接收机接收。在接收模块中，输入到解调器的已调制RF载波只有功率大到能压倒噪声功率时才能被解调出来。一般来说，输入到解调器的RF 信号和噪声功率的比至少要大于10dB。因此RF 信号在解调前必须进行功率传输或操作。调制后的数字类型信息是RF 信号解调后的基带信号。数字信号不需要功率传输，但必须在模块之间进行状态传输，以进行数字信号处理。总之，数字数据传输速度比较低时，RF 信号是功率传输类型的，数字信号是状态传输类型的，这是调制器和解调器实际工程设计所要求的。Lecture 2Richard Li,20117Figure1DemarcationlineinacommunicationsystemRFDigitalBasebandBlocksDigital/AnalogCircuitDesignRFCircuitDesign(a)ReceiverDemarcationlineRF Blocks解调器解调器Digital/AnalogRFDigitalBasebandSection(b)TransmitterRF Blocks调制器调制器Digital/AnalogDigital/AnalogCircuitDesignRFCircuitDesignDemarcationlineLecture 2Richard Li,20118当数字电路工作在低速时，RF 和数字电路的设计方法完全不同。RF 设计工程师关心阻抗匹配，而数字电路工程师对此漠不关心。在电路仿真上，RF 设计工程师更倾向于在频域上仿真，而数字电路工程师主要在时域上做仿真。相对应的，在测试实验室里，RF设计工程师使用频谱或网络分析仪，数字电路工程师使用示波器。Lecture 2Richard Li,20119o情形情形2：高速数字电路：高速数字电路whereR=Transmitteddigitalbitspersecond,fRF=RFcarrierfrequency.20 世纪90 年代电子工业的飞速发展，在很多通信系统，如千兆以太网的传输模块和10Gbps 光传输等模块中，数字电路的传输速率得到极大的提升。高速数字电路与RF电路的区别如下表。ItemItemRFRF电路电路数字电路数字电路ImpedanceImpedanceLow(50 Low(50 typically)typically)Low to high Low to high CurrentCurrentHigh(High(mAmA)Low (Low (AA)to high(mA)to high(mA)在无线通信系统中的位置在无线通信系统中的位置 RxRxFront end(Front end(解调器之前解调器之前)Back end(Back end(解调器之后解调器之后)Tx TxBack end(Back end(调制器之后调制器之后)Front end(Front end(调制器之前调制器之前)Transportation typeTransportation typePower(Power(WattWatt)Status(Voltage or current)Status(Voltage or current)Impedance matchingImpedance matchingImportantImportantImportantImportantBandwidthBandwidth窄带或中带窄带或中带宽带宽带Lecture 2Richard Li,201110在高速数字电路的情形下，这两种电路的任务还是没有改变，RF 电路仍然处理功率，数字电路仍然进行状态的传输和操作。然而，RF 电路和数字电路设计方法上的差别消失了，因为在高速状态下，只有有效地传输和操作功率才能有效地进行传输状态。而且，在高速状态下，当数字速率达到甚至超过RF 频率时，数字电路的阻抗匹配比RF 电路还重要，原因是数字信号是方波脉冲，射频信号一般是正弦波。前者包含很宽的频谱（宽带），后者的频谱相对较窄（窄带）。设计高速数字电路必须关注阻抗匹配。未进行阻抗匹配的高速数字模块的数字电平会受到额外的衰减、抖动、串扰，甚至出现误码。他们必须认真对待PCB设计。低速数字电路的PCB设计中，信号线可以相互平行，这样版图整体感觉整齐美观。然而高速数字电路必须与RF 电路一样认真对待，就像RF 电路，高速数字电路的信号线也会与电路器件或正在工作的电路一样受到串扰。相互平行的信号线会产生额外的电感、电容，甚至相互串扰。数字电路阻抗的高低取决于电路的功能和线路结构。为了节省功耗，大部分数字电路的阻抗都很高。然而，为了阻抗匹配，有些数字电路模块的输入输出阻抗需要降低。为了保证高速传输和工作，必须增加数字电路的电源电流。当电源电流增加到mA 数量级时，数字电路的数据速率可以接近甚至超过射频信号的频率，如果电源电流仍然保持在uA 数量级，大部分数字电路模块的数据速率将远低于射频信号的频率。Lecture 2Richard Li,201111o思考思考 阻抗匹配阻抗匹配 关键参数关键参数Testing*电压、功率反射在电路中真实存在吗?*IC芯片是否因为尺寸小，所以反射并不存在?*数字电路的关键参数：电压?电流?*数字电路和RF电路的测试仪器：示波器和网络分析仪*标量电压和矢量电压的测量？*阻抗匹配对于降低电压、功率损失的必要性.*RF电路的关键参数：功率?阻抗?Lecture 2Richard Li,201112问题问题 Q:为什么数字电路传输的是状态（电压、电流），而为什么数字电路传输的是状态（电压、电流），而RF电路传输的是电路传输的是功率？功率？A:见第见第6页页.数字电路和数字电路和RF电路设计方法不同，源于不同电路设计方法不同，源于不同的设计任务。的设计任务。结论结论Lecture 2Richard Li,201113Q:为什么阻抗匹配在为什么阻抗匹配在RF电路中如此重要，但在低速数字电路电路中如此重要，但在低速数字电路显得并不重要？显得并不重要？A:如果如果RF电路不做阻抗匹配，将产生如下影响：电路不做阻抗匹配，将产生如下影响：*额外的衰减额外的衰减,*额外的失真额外的失真,or额外的串扰额外的串扰*额外的信噪比损失额外的信噪比损失.就算不做阻抗匹配就算不做阻抗匹配,数字信号也能有效地传输，因为线路的阻抗很高，处于一种数字信号也能有效地传输，因为线路的阻抗很高，处于一种半匹配的状态。半匹配的状态。Lecture 2Richard Li,201114Q:为什么阻抗匹配在高速数字电路为什么阻抗匹配在高速数字电路和和RF电路同等重要电路同等重要?A:*高速数字电路不再是高阻抗高速数字电路不再是高阻抗;*如果阻抗匹配并且如果阻抗匹配并且ZSRS.低速数字电路输入输出阻抗通常很高，而高速数字电路的输入输出阻抗不再高，因为晶体管存在输入输出电容，4)High impedance is beneficial to the power transportation or manipulation because,for a definitive voltage,the power becomes high if the impedance is low(say,50).On the contrary,low impedance is beneficial to the status transportation because,for a definitive current,the voltage swing becomes large if the impedance is high.Lecture 2Richard Li,2011185)The task of RF circuit design is power transportation.Power is a product of voltage and current so that it contains two parameters.Rather than two parameters to be taken care,impedance is considered to be the main parameter in the RF circuit design because impedance matching ensures the good power transportation.6)Why is the normalized impedance regulated as 50?(Refer to Thomas H.Lee,“The Design of CMOS Radio-Frequency Integrated Circuits”,(Book),Cambridge University Press,1998).7)It can be tabulated as follows:For a RF signal (if it is considered to be a sinusoidal signal.)Operating frequency 10 100 1000 10000 MHz Input impedance100000100001000100 For a digital signal(if its second and third harmonic are the same important as the main frequency)main frequency)Operating frequency 310 3100 31000 310000 MHz Input impedance333333333333338)The RF signal is a modulated carrier.It can be effectively modulated,transmitted,transported,and de-modulated,only when it has enough power.The ratio of RF signal to noise power at the input of the demodulator is required to be more than 10 dB usually.Therefore,The power transportation or manipulation but not voltage transportation or manipulation is required in the RF block before the demodulator in a receiver and after the modulator in the transmitter.On the contrary,the voltage or current represents the status of digital signal directly.The power of digital signal is expected to be reduced down as much as possible.Therefore,The voltage transportation or manipulation but not power transportation or manipulation is required in the digital/analog blocks,after demodulator in a receiver or before the modulator in a transmitter.Lecture 2Richard Li,2011199)When Wiithout impedance matching,the RF signal would be suffered with *Additional attenuation,*Additional distortion,or additional cross-talk,and eventually *Additional reduction of signal to noise ratio.Without impedance matching,the digital signal would be transported effectively because the impedance of the circuitry is always high,which is in“quasi-impedance matched”state.10)When *Impedance in digital circuit is not longer high;*Voltage transportation gets big advantage if impedance is matched and ZSZL;*The impedance matching even becomes important for a digital circuit more than for a RF circuit if because The waveform of digital signal is rectangular pulse while that of RF signal is sinusoidal usually.Consequently,the digital signal is wide band signal while the RF signal is narrow band signal.*Without impedance matching,the digital voltage level would be suffered with additional attenuation,additional jitter,or additional cross-talk,and eventually additional bit error.Lecture 2Richard Li,2011202.VoltagedeliveredfromasourcetoaloadoGeneralexpressionofvoltagedeliveredfromsourcetoload Figure 1 Voltage delivered from a source to a loadSLZoRSXS ZSSourcePSvS XL ZLLoadRLLRvIfIfIfIf,then,then,then,thenIfthenLecture 2Richard Li,201121tl(Delay time=Td)SourceLoadFigure 2 Voltages bouncing back and forth arrive at load when t=Td.Note:kv=RL/(ZS+ZL)VoltagedeliveredfromSource:VoltagedeliveredfromSource:-12Td -11Td VoltagedeliveredfromSource:VoltagedeliveredfromSource:-10Td -9Td -8Td 2Td 1Td -1Td 0-3Td -2Td -5Td -4Td -7Td -6Td VoltagedeliveredfromSource:Voltagedeliveredfromsource:VoltagedeliveredfromSource:VoltagearrivedatRL,Lecture 2Richard Li,201122NotethatIfthenNotethatLecture 2Richard Li,201123,oAdditionalJitterorDistortioninaDigitalCircuitBlockLecture 2Richard Li,201124Table 1 Additional distortion and additional jitter in voltage transportation when f=3.86 GHz S,%L,%D,%f,GHzT,ns Jitter,%Jitter,ps000.00 3.86 0.2590.000500.00 3.860.2590.0001000.00 3.860.2590.0002000.00 3.860.2590.0005000.00 3.860.2590.000050.003.860.2590.000550.253.860.2590.250.61050.503.860.259 0.501.32051.013.860.2591.012.65052.563.860.2592.566.60100.003.860.2590.0005100.503.860.2590.501.3 10101.013.860.2591.012.620102.043.860.2592.045.350105.263.860.259 5.2613.60200.003.860.259 0.0005201.013.860.2591.012.610202.043.860.2592.045.320204.173.860.2594.1710.8502011.13.860.25911.128.80500.003.860.2590.0005502.563.860.2592.566.6410505.263.860.2595.2613.6205011.13.860.25911.128.8505033.33.860.25933.386.4Lecture 2Richard Li,201125,and then,1)when,and then,2)when ,and then,3)when Thevoltagereflectionbecomespernicious.Thevoltagereflectionseemsnottooharmful.Thevoltagereflectionishorrible!Lecture 2Richard Li,2011263.PowerdeliveredfromasourcetoaloadoGeneralexpressionofpowerdeliveredfromsourcetoloadFigure 3 Power delivered from a source to a loadSLZoRSXS ZSSourcePSvS XL ZLLoadRLIfIfIfIf,then,then,then,thenIfthenLRvLecture 2Richard Li,201127tl(Delay time=Td)SourceLoadFigure 4 Powers bounce forth and back and arrive at load when t=Td.(Note:kp=RL/|ZS+ZL|2)Powerdeliveredfromsource:Powerdeliveredfromsource:-12Td -11Td Powerdeliveredfromsource:Powerdeliveredfromsource:-10Td -9Td -8Td 2Td 1Td -1Td 0-3Td -2Td -5Td -4Td -7Td -6Td Powerdeliveredfromsource:Powerdeliveredfromsource:Powerdeliveredfromsource:PowerarrivedatRL,Lecture 2Richard Li,201128oPowerInstabilityNotethatIfthenLecture 2Richard Li,201129oAdditionalPowerLossLecture 2Richard Li,201130 Table 2 Additional power loss due to the unmatched case when =-30 dBm.S,%L,%,dBm,dBm,dBm000.0000-30-infinite-30500.0000-30-infinite-301000.0000-30-infinite-302000.0000-30-infinite-305000.0000-30-infinite-30050.0500-30-43.01-30.22550.0476-30-43.22-30.211050.0452-30-43.45-30.202050.0404-30-43.94-30.185050.0256-30-45.91-30.110100.1000-30-40.00-30.465100.0955-30-40.20-30.4410100.0909-30-40.41-30.4120100.0816-30-40.88-30.3750100.0526-30-49.79-30.23 0200.2000-30-36.99-30.975200.1919-30-37.17-30.9310200.1837-30-37.36-30.8820200.1667-30-37.78-30.7950200.1111-30-35.40-30.510500.5000-30-33.01-33.015500.4872-30-33.12-39.9010500.4737-30-33.25-39.7920500.4444-30-33.52-39.5550500.3333-30-34.77-31.76Lecture 2Richard Li,201131oAdditionalDistortionNotethatLecture 2Richard Li,201132Table 3 Additional distortion in power transportation S,%L,%Dp,%000.00 500.00 1000.00 2000.00 5000.00 0529.365521.8210521.2720520.1050516.0101031.6251030.90101030.15201028.57501029.94 02044.7252043.81102049.86202040.82502033.3305070.7155068.00105068.82205066.67505057.74Lecture 2Richard Li,201133From Table 3 it can be seen that In cases where L=0,there is no additional distortion.On the contrary,in the cases of L 0,the additional distortion is appreciable!The additional distortion is more sensitive to the value of L than to the value of S,For given value of L,the additional distortion is somewhat reduced as the value of S is increased.For given value of S,the additional distortion is somewhat increased as the value of L is increased.The highest value of the additional distortion in Table 3 is 70.71%when S=0 and L=50%.Lecture 2Richard Li,201134oAdditionalInterferenceLecture 2Richard Li,201135 Table 4 Calculated ratio of signal to interference as the reflection coefficient,is varied.S,L,%dB W%W W dB0015 31.620.00000.00001.0015.005015 31.62 0.00000.00001.0015.0010015 31.620.00000.00001.0015.0020015 31.620.00000.00001.0015.0050015 31.62 0.00000.00001.0015.000515 31.620.00000.00001.0015.005515 31.620.00250.00251.0814.6710515 31.620.00500.00501.1614.3620515 31.620.01000.01011.3213.8050515 31.620.02500.02561.8112.4201015 31.620.00000.00001.0015.0051015 31.620.00500.00501.1614.36101015 31.620.01000.01011.3213.80201015 31.620.02000.02041.6512.84501015 31.620.05000.05262.6610.7402015 31.620.00000.00001.0015.0052015 31.620.01000.01011.3213.80102015 31.620.02000.02041.6512.84202015 31.620.04000.04172.3211.35502015 31.620.10000.11114.51 8.4505015 31.620.00000.00001.0015.0055015 31.620.02500.02561.8112.42105015 31.620.05000.05262.6610.74205015 31.620.10000.11114.51 8.45505015 31.620.25000.333311.54 4.38 Lecture 2Richard Li,201136From Table 4 it can be seen that In cases where L=0,there is no additional interference,so the SIR is kept unchanged.The additional interference is more sensitive to the value of L than to the value of S,For a given value of L,the additional interference increases as the value of S increases so that the SIR is reduced.For a given value of S,the additional interference increases as the value of L increases so that the SIR is reduced.The highest value of the additional interference in Table 9.4 is reached when S=50%and L=50%.At this point the SIR drops from 15 dB to 4.38 dB.Lecture 2Richard Li,201137 oMaximizingofPowerTransportation ,or,or,or,4.ImpedanceConjugateMatchingFigure 5 Power delivered from a source to a load without reflectionS=0L=0ZoRSXS ZSSourcePSvS XL ZLLoadRLLecture 2Richard Li,201138Thisiscalled“neutralization”ofreactancebetweensourceandload.oPowerTransportationwithoutPhaseShiftFigure 6 Two matching cases when reactance of source is“neutralized”by reactance of load,or,vice versa,that is,XS=-XL(a)RSinserieswithXS(b)RSinparallelwithXS RLinserieswithXLRLinparallelwithXLRSRLvS vLXSXL“Neutralization”ofreactanceRSRLvL XLXS“Neutralization”ofreactancevS Lecture 2Richard Li,201139(c)8PSK(b)4PSK(a)BPSK(e)16QAM(f)64QAM9.46oFigure 7 Progress of modulation technology from PSK to QAM(d)16PSK22.5o26.56oLecture 2Richard Li,201140Lecture 2Richard Li,201141 Amatchingnetworkmustbeinsertedbetweensourceandloadsothattheimpedancematchingconditioncanbesatisfiedasfollowing:oImpedanceMatchingNetworkUsuallyRSvSXSSourcePSXLRLLoadFigure 8 An impedance matching network is inserted between source and load when