电子技术-芯片资料-74HC112.pdf

TL/F/5307MM54HC112/MM74HC112 Dual J-K Flip-Flops with Preset and ClearJanuary 1988MM54HC112/MM74HC112Dual J-K Flip-Flops with Preset and ClearGeneral DescriptionThese high speed(30 MHz minimum)J-K Flip-Flops utilizeadvanced silicon-gate CMOS technology to achieve the lowpower consumption and high noise immunity of standardCMOS integrated circuits,along with the ability to drive 10LS-TTL loads.Each flip-flop has independent J,K,PRESET,CLEAR,andCLOCK inputs and Q and Q outputs.These devices areedge sensitive to the clock input and change state on thenegative going transition of the clock pulse.Clear and pre-set are independent of the clock and accomplished by a lowlogic level on the corresponding input.The 54HC/74HC logic family is functionally as well as pin-out compatible with the standard 54LS/74LS logic family.All inputs are protected from damage due to static dis-charge by internal diode clamps to VCCand ground.FeaturesYTypical propagation delay:16 nsYWide operating voltage rangeYLow input current:1 mA maximumYLow quiescent current:40 mA(74HC Series)YHigh output drive:10 LS-TTL loadsConnection and Logic DiagramsDual-In-Line PackageTL/F/53071Top ViewOrder Number MM54HC112 or MM74HC112Truth TableInputsOutputsPRCLRCLKJKQQLHXXXHLHLXXXLHLLXXXL*L*HHvLLQ0Q0HHvHLHLHHvLHLHHHvHHTOGGLEHHHXXQ0Q0*This is an unstable condition,and is not guaranteedTL/F/53072TL/F/53073C1995 National Semiconductor CorporationRRD-B30M105/Printed in U.S.A.Absolute Maximum Ratings(Notes 1&2)If Military/Aerospace specified devices are required,pleasecontacttheNationalSemiconductorSalesOffice/Distributors for availability and specifications.Supply Voltage(VCC)b0.5 toa7.0VDC Input Voltage(VIN)b1.5 to VCCa1.5VDC Output Voltage(VOUT)b0.5 to VCCa0.5VClamp Diode Current(IIK,IOK)g20 mADC Output Current,per pin(IOUT)g25 mADC VCCor GND Current,per pin(ICC)g50 mAStorage Temperature Range(TSTG)b65C toa150CPower Dissipation(PD)(Note 3)600 mWS.O.Package only500 mWLead Temp.(TL)(Soldering 10 seconds)260COperating ConditionsMinMaxUnitsSupply Voltage(VCC)26VDC Input or Output Voltage0VCCV(VIN,VOUT)Operating Temp.Range(TA)MM74HCb40a85CMM54HCb55a125CInput Rise or Fall TimesVCCe2.0V(tr,tf)1000nsVCCe4.5V500nsVCCe6.0V400nsDC Electrical Characteristics(Note 4)TAe25C74HC54HCSymbolParameterConditionsVCCTAeb40 to 85CTAeb55 to 125CUnitsTypGuaranteed LimitsVIHMinimum High Level2.0V1.51.51.5VInput Voltage4.5V3.153.153.15V6.0V4.24.24.2VVILMaximum Low Level2.0V0.50.50.5VInput Voltage*4.5V1.351.351.35V6.0V1.81.81.8VVOHMinimum High LevelVINeVIHor VILOutput VoltagelIOUTls20 mA2.0V2.01.91.91.9V4.5V4.54.44.44.4V6.0V6.05.95.95.9VVINeVIHor VILlIOUTls4.0 mA4.5V4.23.983.843.7VlIOUTls5.2 mA6.0V5.75.485.345.2VVOLMaximum Low LevelVINeVIHor VILOutput VoltagelIOUTls20 mA2.0V00.10.10.1V4.5V00.10.10.1V6.0V00.10.10.1VVINeVIHor VILlIOUTls4.0 mA4.5V0.20.260.330.4VlIOUTls5.2 mA6.0V0.20.260.330.4VIINMaximum InputVINeVCCor GND6.0Vg0.1g1.0g1.0mACurrentICCMaximum QuiescentVINeVCCor GND6.0V4.04080mASupply CurrentIOUTe0 mANote 1:Absolute Maximum Ratings are those values beyond which damage to the device may occur.Note 2:Unless otherwise specified all voltages are referenced to ground.Note 3:Power Dissipation temperature derating plastic N package:b12 mW/C from 65C to 85C;ceramic J package:b12 mW/C from 100C to 125C.Note 4:For a power supply of 5Vg10%the worst case output voltages(VOH,and VOL)occur for HC at 4.5V.Thus the 4.5V values should be used when designingwith this supply.Worst case VIHand VILoccur at VCCe5.5V and 4.5V respectively.(The VIHvalue at 5.5V is 3.85V.)The worst case leakage current(IIN,ICC,andIOZ)occur for CMOS at the higher voltage and so the 6.0V values should be used.*VILlimits are currently tested at 20%of VCC.The above VILspecification(30%of VCC)will be implemented no later than Q1,CY89.2AC Electrical CharacteristicsVCCe5V,TAe25C,CLe15 pF,tretfe6 nsSymbolParameterConditionsTypGuaranteed LimitUnitsfMAXMaximum Operating5030MHzFrequencytPHL,tPLHMaximum Propagation1621nsDelay,Clock to Q or QtPHL,tPLHMaximum Propagation2126nsDelay,Clear to Q or QtPHL,tPLHMaximum Propagation2328nsDelay,Preset to Q or QtREMMinimum Removal Time,1020nsPreset or Clear to ClocktsMinimum Setup Time1420nsJ or K to ClocktHMinimum Hold Timeb30nsJ or K from ClocktWMinimum Pulse Width1016nsClock Preset or ClearAC Electrical CharacteristicsCLe50 pF,tretfe6 ns(unless otherwise specified)TAe25C74HC54HCSymbolParameterConditionsVCCTAeb40 to 85CTAeb55 to 125CUnitsTypGuaranteed LimitsfMAXMaximum Operating2.0V9543MHzFrequency4.5V45272118MHz6.0V53312420MHztPHL,tPLHMaximum Propagation2.0V100126160183nsDelay,Clock to Q or Q4.5V20253237ns6.0V17212732nstPHL,tPLHMaximum Propagation2.0V126155191250nsDelay,Clear to Q or Q4.5V25313947ns6.0V21263340nstPHL,tPLHMaximum Propagation2.0V137165210240nsDelay,Preset to Q or Q4.5V27334150ns6.0V23283540nstREMMinimum Removal Time2.0V55100125150nsPreset or Clear4.5V11202530nsto Clock6.0V9.4172125nstsMinimum Setup Time2.0V77100125150nsJ or K to Clock4.5V15202530ns6.0V13172125nstHMinimum Hold Time2.0Vb3000nsJ or K from Clock4.5Vb3000ns6.0Vb3000nstWMinimum Pulse Width2.0V5580100120nsPreset,Clear or Clock4.5V11162024ns6.0V9141820nstTLH,tTHLMaximum Output Rise2.0V307595110nsand Fall Time4.5V8151922ns6.0V7131619nstr,tfMaximum Input Rise and2.0V100010001000nsFall Time4.5V500500500ns6.0V400400400nsCPDPower Dissipation(per flip-flop)80pFCapacitance(Note 5)CINMaximum Input Capacitance5101010pFNote 5:CPDdetermines the no load dynamic power consumption,PDeCPDVCC2faICCVCC,and the no load dynamic current consumption,ISeCPDVCCfaICC.3Typical ApplicationsN Bit Presettable Ripple Counter with Enable and ResetTL/F/53074N Bit Parallel Load/Serial Load Shift Register with ClearTL/F/5307545MM54HC112/MM74HC112 Dual J-K Flip-Flops with Preset and ClearPhysical Dimensionsinches(millimeters)Ceramic Dual-In-Line Package(J)Order Number MM54HC112J or MM74HC112JNS Package Number J16AMolded Dual-In-Line Package(N)Order Number MM74HC112NNS Package Number N16ELIFE SUPPORT POLICYNATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONALSEMICONDUCTOR CORPORATION.As used herein:1.Lifesupportdevicesorsystemsaredevicesor2.A critical component is any component of a lifesystems which,(a)are intended for surgical implantsupport device or system whose failure to perform caninto the body,or(b)support or sustain life,and whosebe reasonably expected to cause the failure of the lifefailure to perform,when properly used in accordancesupport device or system,or to affect its safety orwith instructions for use provided in the labeling,caneffectiveness.be reasonably expected to result in a significant injuryto the user.National SemiconductorNational SemiconductorNational SemiconductorNational SemiconductorCorporationEuropeHong Kong Ltd.Japan Ltd.1111 West Bardin RoadFax:(a49)0-180-530 85 8613th Floor,Straight Block,Tel:[phone]Arlington,TX 76017Email:Ocean Centre,5 Canton Rd.Fax:[phone]Tel:[phone]Deutsch Tel:(a49)0-180-530 85 85Tsimshatsui,KowloonFax:1(800)737-7018EnglishTel:(a49)0-180-532 78 32Hong KongFran3ais Tel:(a49)0-180-532 93 58Tel:[phone]ItalianoTel:(a49)0-180-534 16 80Fax:[phone]National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.