资源描述
电子综合设计
基于FPGA的四路智能抢答器
目录
1． 设计目的
2． 抢答器的特点
3． 设计的内容要求
4． 系统硬件原理图
5． 软件流程图
6． 系统电路图
7． 系统各模块设计分析
8． 原程序代码
9． 设计感想
10． 参考文献
11． 附录
一、设计目的：
通过本次电子综合设计，掌握了数字电路系统的设计方法，进一步学会了如何使用数字电路实现现实的电路系统；学会了如何运用硬件描述语言VHDL驱动数字硬件电路的工作，实现软硬件连调，以达到软硬件协同工作的目的；加强自主动手制作硬件以及编程实现所需现实功能的能力；
二、抢答器的特点
抢答器是为智力竞赛参赛者答题时进行抢答而设计的一种优先判决器电路，广泛应用于各种知识竞赛、文娱活动等场合。在各类竞赛中，特别是做抢答题时，在抢答过程中，为了知道哪一组或哪一名选手先答题，必须要有一个系统来完成这个任务。抢答过程中，只靠人的视觉是很难判断出哪组先答题。利用FPGA数字电路来设计抢答器，则可轻松解决这个问题。
够实现抢答器功能的方式有多种，可以采用模拟电路、数字电路或模拟与数字电路相结合的方式。早期的抢答器只由几个三极管、可控硅、发光管等组成， 能通过发光管的指示辨认出选手号码。现在大多数抢答器均使用数字集成电路，并增加了许多新功能，如选手号码显示、抢按前或抢按后的计时、选手得分显示功能。像这类抢答器，制作过程简单，准确性与可靠性高，而且安装维护简单。随着电子技术的发展，现在的抢答器功能越来越强，可靠性和准确性也越来越高。
三、设计的内容要求：
1. 设计一个智力抢答系统，可同时四名选手参加比赛，对应四个抢答按钮。
2.设置主持人控制键，包括开始、复位、加分、减分键。
3.倒计时系统，当主持人按开始键后，进行10s的倒计时抢答时间并在后5s开始蜂鸣报警，若无人抢答，开始下一题；若有选手抢答，该选手对应的指示灯熄灭，并进行30s的答题倒计时，并在后5s开始蜂鸣报警，由主持人加减选手的分，并开始下一题。
4.若违规操作，减一分。
四、系统硬件原理图
FPGA
EP2C8Q208C8N
按键
L
E
D
灯
LED
数码管
蜂鸣器
本次设计中使用了LB1板子上的资源有：四个按键，4个led灯，6个数码管，蜂鸣器，芯片138，芯片244.
五、软件流程图
开始
初始状态（数码管显示各组分数，LED灯熄，数码管显示时间0）
各组按键抢答
抢答到or
违规
抢答到
按下start键
10s倒计时，最后5s蜂鸣报警
每组对应的LED灯点熄，开始30s倒计时，最后5s蜂鸣器发声，其他各组按键无效
违规
在start键按下之前抢答
回答是否
正确
对应的组得分减一分
回答错误
对应组的LED灯亮
对应的组得分加一分
回答正确
是否有组抢答
有组抢答
无组抢答
按下start键进入下一轮抢答
结束
流程说明：首先，下载程序后显示开机动画；当打开运行开关后，显示主界面，通过配置开关来控制LCD的分页。LCD液晶屏主要显示五个分页，包括开机动画、组员和老师介绍、问题提问、分数显示及胜利选手恭喜界面。而抢答器的控制流程具体如下，首先在开始时clear和start按键置低，准备比赛开始；选择题目，四组选手通过四个按键进行抢答。抢答前有3秒准备时间，时间结束后开始抢答，否则视为犯规，自动扣一分；且抢答犯规者的LED灯闪亮，抢到者的LED灯常亮。选手抢到后，有8秒的回答时间，通过小键盘输入选择答案，由裁判主持人进行答案的判断和加减分控制；如8秒结束后选手为作答，则自动扣一分，并显示出正确答案。每轮问题结束后，自动统计每组选手和分数。Clear按键按下，重新开始下一轮提问，start按键按下，开始抢答。当比赛结束后，开关控制显示最高分者为胜出，有胜出界面，同时播放语音恭喜音乐。
六、系统电路图：
七、系统各模块设计分析：
1.分频模块
该模块对50MHZ的时钟分频，给其他模块提供相应的参考时钟，
2.去抖模块
由于机械按键会产生抖动，而抖动的上下沿在数字系统中比较敏感，容易产生毛刺甚至使系统产生无法预料的结果。所以必须进行按键去抖。
仿真波形：
3.控制模块
仿真波形：
4.延迟模块
仿真波形：
5.蜂鸣器
该模块实现蜂鸣器报警提醒功能。
仿真波形：
6.显示模块
该模块为显示LED显示模块。通过动态扫描同时显示几位LED。其中输出led_a—led_g及dp段选，led_wei[5..0]为位选码，控制焊接的4个数码管来显示各组的分数，另外2个显示时间
仿真波形：
八、原程序代码：
1.分频模块：
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY CLOCK IS
PORT(CLK_50MHz:IN STD_LOGIC;
CLK_1MHZ:OUT STD_LOGIC;
CLK_2KHZ:OUT STD_LOGIC;
CLK_1KHZ:OUT STD_LOGIC;
CLK_100HZ:OUT STD_LOGIC;
CLK_5HZ: OUT STD_LOGIC;
CLK_1HZ: OUT STD_LOGIC
);
END;
ARCHITECTURE BEHAV OF CLOCK IS
SIGNAL Q1,Q2,Q3,Q4,Q5,Q6 : STD_LOGIC;
SIGNAL COUNT1: INTEGER RANGE 25 DOWNTO 0;
SIGNAL COUNT2: INTEGER RANGE 12500 DOWNTO 0;
SIGNAL COUNT3: INTEGER RANGE 25000 DOWNTO 0;
SIGNAL COUNT4: INTEGER RANGE 250000 DOWNTO 0;
SIGNAL COUNT5: INTEGER RANGE 5000000 DOWNTO 0;
SIGNAL COUNT6: INTEGER RANGE 25000000 DOWNTO 0;
BEGIN
PROCESS(CLK_50MHz)
BEGIN
IF CLK_50MHz'EVENT AND CLK_50MHz='0'THEN
IF COUNT1=24 THEN
COUNT1<=0;
Q1<=NOT Q1;
ELSE
COUNT1<=COUNT1+1;
END IF;
------------------------------------------
IF COUNT2=12499 THEN
COUNT2<=0;
Q2<=NOT Q2;
ELSE
COUNT2<=COUNT2+1;
END IF;
------------------------------------------
IF COUNT3=24999 THEN
COUNT3<=0;
Q3<=NOT Q3;
ELSE
COUNT3<=COUNT3+1;
END IF;
------------------------------------------
IF COUNT4=249999 THEN
COUNT4<=0;
Q4<=NOT Q4;
ELSE
COUNT4<=COUNT4+1;
END IF;
------------------------------------------
IF COUNT5=5999999 THEN
COUNT5<=0;
Q5<=NOT Q5;
ELSE
COUNT5<=COUNT5+1;
END IF;
------------------------------------------
IF COUNT6=25999999 THEN
COUNT6<=0;
Q6<=NOT Q6;
ELSE
COUNT6<=COUNT6+1;
END IF;
END IF;
CLK_1MHZ<=Q1;
CLK_2KHZ<=Q2;
CLK_1KHZ<=Q3;
CLK_100HZ<=Q4;
CLK_5HZ<=Q5;
CLK_1HZ<=Q6;
END PROCESS;
END BEHAV;
2.去抖模块：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned;
entity shuru is
port(clk_1kHz:in std_logic;
reset:in std_logic;
start:in std_logic;
sub:in std_logic;
add:in std_logic;
NUM1:in std_logic;
NUM2:in std_logic;
NUM3:in std_logic;
NUM4:in std_logic;
St:out std_logic;
Re:out std_logic;
AD:out std_logic;
Su:out std_logic;
NUM:out std_logic_vector(3 downto 0)
);
end entity shuru;
architecture behav of shuru is
signal count1,count2,count3,count4,count5,count6,count7,count8:integer range 0 to 10000;
begin
process(clk_1kHz,reset,start,add,sub,NUM1,NUM2,NUM3,NUM4)
begin
if clk_1kHz'event and clk_1kHz='1' then
---------------------------------------------
if start='1' then
count1<=0;
else
count1<=count1+1;
end if;
if count1>20 and count1<70 then
St<='0';
else
St<='1';
end if;
---------------------------------------------
if reset='1' then
count2<=0;
else
count2<=count2+1;
end if;
if count2>20 and count2<70 then
Re<='0';
else
Re<='1';
end if;
-------------------------------------------
if add='1' then
count3<=0;
else
count3<=count3+1;
end if;
if count3>20 and count3<70 then
AD<='0';
else
AD<='1';
end if;
-----------------------------------------
if sub='1' then
count4<=0;
else
count4<=count4+1;
end if;
if count4>20 and count4<70 then
Su<='0';
else
Su<='1';
end if;
-----------------------------------------
if NUM1='1' then
count5<=0;
else
count5<=count5+1;
end if;
if count5>20 and count5<70 then
NUM(0)<='1';
else
NUM(0)<='0';
end if;
----------------------------------------
if NUM2='1' then
count6<=0;
else
count6<=count6+1;
end if;
if count6>20 and count6<70 then
NUM(1)<='1';
else
NUM(1)<='0';
end if;
----------------------------------------
if NUM3='1' then
count7<=0;
else
count7<=count7+1;
end if;
if count7>20 and count7<70 then
NUM(2)<='1';
else
NUM(2)<='0';
end if;
----------------------------------------
if NUM4='1' then
count8<=0;
else
count8<=count8+1;
end if;
if count8>20 and count8<70 then
NUM(3)<='1';
else
NUM(3)<='0';
end if;
---------------------------------------
end if;
end process;
end behav;
3.控制模块:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Control IS
PORT(START:IN STD_LOGIC;
RESET:IN STD_LOGIC;
ADD: IN STD_LOGIC;
SUB: IN STD_LOGIC;
NUM : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_TIME:IN STD_LOGIC;
CLK_1MHz:IN STD_LOGIC;
DEL_PRE :OUT STD_LOGIC;
DEL_ANS :OUT STD_LOGIC;
LED : OUT STD_LOGIC_VECTOR(3 downto 0);
SCORE1:OUT STD_LOGIC_VECTOR(3 downto 0);
SCORE2:OUT STD_LOGIC_VECTOR(3 downto 0);
SCORE3:OUT STD_LOGIC_VECTOR(3 downto 0);
SCORE4:OUT STD_LOGIC_VECTOR(3 downto 0)
);
END;
ARCHITECTURE BEHAV OF Control IS
TYPE STATE IS (S0,S1,S2);
SIGNAL CURRENT_STATE,NEXT_STATE:STATE;
SIGNAL SCORE1_MID:STD_LOGIC_VECTOR(3 downto 0);
SIGNAL SCORE2_MID:STD_LOGIC_VECTOR(3 downto 0);
SIGNAL SCORE3_MID:STD_LOGIC_VECTOR(3 downto 0);
SIGNAL SCORE4_MID:STD_LOGIC_VECTOR(3 downto 0);
SIGNAL SCORE:STD_LOGIC_VECTOR(3 downto 0);
SIGNAL SCORE_ADD:STD_LOGIC;
SIGNAL SCORE_SUB:STD_LOGIC;
SIGNAL SCORE_CLK:STD_LOGIC;
SIGNAL NUM_STORE:STD_LOGIC_VECTOR(3 downto 0);
BEGIN
-------------------------------------------------------------------
PROCESS(RESET,CLK_1MHz)
BEGIN
IF RESET='0' THEN
CURRENT_STATE<=S0;
ELSIF CLK_1MHz='1' AND CLK_1MHz'EVENT THEN
CURRENT_STATE<=NEXT_STATE;
END IF;
END PROCESS;
-------------------------------------------------------------------
PROCESS(CURRENT_STATE,NEXT_STATE,CLK_1MHz,NUM,START,OUT_TIME,ADD,SUB)
BEGIN
CASE CURRENT_STATE IS
WHEN S0 => DEL_PRE<='1';
DEL_ANS<='1';
LED<="0000";
SCORE_SUB<='0';
SCORE_ADD<='0';
IF START='0' THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S0;
END IF;
WHEN S1 => DEL_PRE<='0';
DEL_ANS<='1';
LED<="0000";
SCORE_SUB<='0';
SCORE_ADD<='0';
IF OUT_TIME='0' THEN
NEXT_STATE<=S0;
ELSIF NUM/="0000" THEN
NEXT_STATE<=S2;
NUM_STORE<=NUM;
ELSE
NEXT_STATE<=S1;
END IF;
WHEN S2 => DEL_PRE<='1';
DEL_ANS<='0';
LED<=NUM_STORE;
IF OUT_TIME='0' THEN
SCORE_SUB<='1';
NEXT_STATE<=S0;
ELSIF SUB='0' THEN
SCORE_SUB<='1';
NEXT_STATE<=S0;
ELSIF ADD='0' THEN
SCORE_ADD<='1';
NEXT_STATE<=S0;
ELSE
NEXT_STATE<=S2;
END IF;
END CASE;
END PROCESS;
PROCESS(SCORE_SUB,SCORE_ADD)
BEGIN
SCORE_CLK<=(SCORE_ADD OR SCORE_SUB);
IF SCORE_CLK='1' AND SCORE_CLK'EVENT THEN
IF SCORE_ADD='1' THEN
IF NUM_STORE(0)='1' THEN
SCORE1_MID<=SCORE1_MID+'1';
ELSIF NUM_STORE(1)='1' THEN
SCORE2_MID<=SCORE2_MID+'1';
ELSIF NUM_STORE(2)='1' THEN
SCORE3_MID<=SCORE3_MID+'1';
ELSIF NUM_STORE(3)='1' THEN
SCORE4_MID<=SCORE4_MID+'1';
END IF;
ELSIF SCORE_SUB='1' THEN
IF NUM_STORE(0)='1' THEN
SCORE1_MID<=SCORE1_MID-'1';
ELSIF NUM_STORE(1)='1' THEN
SCORE2_MID<=SCORE2_MID-'1';
ELSIF NUM_STORE(2)='1' THEN
SCORE3_MID<=SCORE3_MID-'1';
ELSIF NUM_STORE(3)='1' THEN
SCORE4_MID<=SCORE4_MID-'1';
END IF;
END IF;
END IF;
SCORE1<=SCORE1_MID;
SCORE2<=SCORE2_MID;
SCORE3<=SCORE3_MID;
SCORE4<=SCORE4_MID;
END PROCESS;
END BEHAV;
4.延迟模块：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DELAY IS
PORT( DEL_PRE :IN STD_LOGIC;
DEL_ANS :IN STD_LOGIC; --GAO DIAN PIN SHI XIANSHI WEI 00, DI DIAN PIN XIANSHI YIMIAO DE YAN SHI;
CLK_100Hz:IN STD_LOGIC;
--CLK_1Hz: OUT STD_LOGIC;
OUT_TIME:OUT STD_LOGIC;
TIME1 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
TIME10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END;
ARCHITECTURE BEHAV OF DELAY IS
SIGNAL CLK_1Hz_PRE: STD_LOGIC;
SIGNAL CLK_1Hz_ANS: STD_LOGIC;
SIGNAL COUNT_PRE:INTEGER RANGE 0 TO 100;
SIGNAL COUNT_ANS:INTEGER RANGE 0 TO 100;
SIGNAL OUT_TIME_PRE: STD_LOGIC;
SIGNAL OUT_TIME_ANS: STD_LOGIC;
SIGNAL COUNT1_PRE,COUNT10_PRE:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNT1_ANS,COUNT10_ANS:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK_100Hz)
BEGIN
IF DEL_PRE='0' THEN
IF CLK_100Hz'EVENT AND CLK_100Hz='1'THEN
IF COUNT_PRE=99 THEN
COUNT_PRE<=0;
CLK_1Hz_PRE<='1';
ELSE
COUNT_PRE<=COUNT_PRE+1;
CLK_1Hz_PRE<='0';
END IF;
END IF;
END IF;
END PROCESS;
---------------------------------------------------------
PROCESS(CLK_100Hz)
BEGIN
IF DEL_ANS='0' THEN
IF CLK_100Hz'EVENT AND CLK_100Hz='1'THEN
IF COUNT_ANS=99 THEN
COUNT_ANS<=0;
CLK_1Hz_ANS<='1';
ELSE
COUNT_ANS<=COUNT_ANS+1;
CLK_1Hz_ANS<='0';
END IF;
END IF;
END IF;
END PROCESS;
----------------------------------------------------------
PROCESS(CLK_1Hz_PRE,DEL_PRE,DEL_ANS)
BEGIN
IF DEL_PRE='0' THEN
IF CLK_1Hz_PRE'EVENT AND CLK_1Hz_PRE='1' THEN
IF COUNT1_PRE="0000" AND COUNT10_PRE="0000" THEN
COUNT1_PRE<="1001";
COUNT10_PRE<="0000";
OUT_TIME_PRE<='0';
ELSIF COUNT1_PRE="0000" THEN
COUNT1_PRE<="1001";
COUNT10_PRE<=COUNT10_PRE-'1';
OUT_TIME_PRE<='1';
ELSE
COUNT1_PRE<=COUNT1_PRE-'1';
OUT_TIME_PRE<='1';
END IF;
END IF;
ELSE
COUNT1_PRE<="1001";
COUNT10_PRE<="0000";
OUT_TIME_PRE<='1';
END IF;
END PROCESS;
PROCESS(CLK_1Hz_ANS,DEL_PRE,DEL_ANS)
BEGIN
IF DEL_ANS='0' THEN
IF CLK_1Hz_ANS'EVENT AND CLK_1Hz_ANS='1' THEN
IF COUNT1_ANS="0000" AND COUNT10_ANS="0000" THEN
COUNT1_ANS<="1001";
COUNT10_ANS<="0010";
OUT_TIME_ANS<='0';
ELSIF COUNT1_ANS="0000" THEN
COUNT1_ANS<="1001";
COUNT10_ANS<=COUNT10_ANS-'1';
OUT_TIME_ANS<='1';
ELSE
COUNT1_ANS<=COUNT1_ANS-'1';
OUT_TIME_ANS<='1';
END IF;
END IF;
ELSE
COUNT1_ANS<="1001";
COUNT10_ANS<="0010";
OUT_TIME_ANS<='1';
END IF;
END PROCESS;
------------------------------------------------------------------------
PROCESS(DEL_PRE,DEL_ANS)
BEGIN
IF DEL_PRE='0' THEN
TIME1<=COUNT1_PRE;
TIME10<=COUNT10_PRE;
OUT_TIME<=OUT_TIME_PRE;
ELSIF DEL_ANS='0' THEN
TIME1<=COUNT1_ANS;
TIME10<=COUNT10_ANS;
OUT_TIME<=OUT_TIME_ANS;
ELSE
TIME1<="0000";
TIME10<="0000";
OUT_TIME<='1';
END IF;
END PROCESS;
END BEHAV;
5.蜂鸣器模块：
library ieee;
use ieee.std_logic_1164
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