中芯国际RD及半导体技术发展趋势.ppt

SMIC Confidential,All copyrights and IP belong to SMIC.For reference only and may not be copied or distributed without written permission from SMIC.SMIC shall not be responsible for any partys reliance on these materials.,*,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,R 29,G 115,B 176,R 69,G 153,B 195,R 0,G 51,B 153,R 190,G 26,B 38,R 234,G 40,B 57,R 255,G 121,B 1,R 155,G 238,B 255,R 146,G 212,B 0,R 205,G 234,B 247,R 254,G 203,B 1,*,R 6,G 30,B 60,R 140,G 140,B 140,R 75,G 75,B 75,R 220,G 220,B 220,SMIC Confidential,All copyrights and IP belong to SMIC.For reference only and may not be copied or distributed without written permission from SMIC.SMIC shall not be responsible for any partys reliance on these materials.,Semiconductor Technology Trends,&SMICs R&D to Supply Manufacturing Technologies,2014,北京微电子国际研讨会,Safe Harbor Statements,Under the Private Securities Litigation Reform Act of 1995,This document contains,in addition to historical information,“forward-looking statements”within the meaning of the“safe harbor”provisions of the U.S.Private Securities Litigation Reform Act of 1995.These forward-looking statements are based on SMICs current assumptions,expectations and projections about future events.SMIC uses words like“believe,”“anticipate,”“intend,”“estimate,”“expect,”“project”and similar expressions to identify forward looking statements,although not all forward-looking statements contain these words.These forward-looking statements are necessarily estimates reflecting the best judgment of SMICs senior management and involve significant risks,both known and unknown,uncertainties and other factors that may cause SMICs actual performance,financial condition or results of operations to be materially different from those suggested by the forward-looking statements including,among others,risks associated with cyclicality and market conditions in the semiconductor industry,intense competition,timely wafer acceptance by SMICs customers,timely introduction of new technologies,SMICs ability to ramp new products into volume,supply and demand for semiconductor foundry services,industry overcapacity,shortages in equipment,components and raw materials,availability of manufacturing capacity,financial stability in end markets and intensive intellectual property litigation in high tech industry.,In addition to the information contained in this document,you should also consider the information contained in our other filings with the SEC,including our annual report on Form 20-F filed with the SEC on April 14,2014,especially in the“Risk Factors”section and such other documents that we may file with the SEC or SEHK from time to time,including on Form 6-K.Other unknown or unpredictable factors also could have material adverse effects on our future results,performance or achievements.In light of these risks,uncertainties,assumptions and factors,the forward-looking events discussed in this document may not occur.You are cautioned not to place undue reliance on these forward-looking statements,which speak only as of the date stated or,if no date is stated,as of the date of this document.,2,Outline,Major Technology Challenges,SMICs Technology R&D Strategies and Plans,Continue to build&enhance high quality and innovative R&D at SMIC,Place significant focus on leading-edge differentiation technologies,Strengthen R&D on advanced CMOS technology,Enrich design IP to actively support design houses for faster TTM,Actively drive the growth in domestic IC industry chain,3.Concluding Remarks,3,国际主流逻辑技术路线图,1H13,2H13,1H14,2H14,1H15,2H15,2H12,1H16,2H16,1H17,2H17,Skip 20nm Planar,14nm,FF,16nm FF,14nm FF,14nm FF,14nm FF,22nm FF,Speculated,14nm FF,Trial/NTO,MP,Foundry,T,GF,U,Samsung,(Intel),国际主流公司未来五年逻辑技术路线图，各公司均加快了科研进度，多数公司在未来五年均拟推出,3,代或,3,代以上技术产品。,20nm Planar,20nm Planar,10nm FinFET,10nm FinFET,10nm FinFET,10nm FinFET,7nm FinFET,7nm FinFET,7nm FinFET,7nm FinFET,Pre-manufacture,Technologies,Manufacture,Technologies,4,我国集成电路产业技术进步,落后,2-3,年,摘自：北京大学王阳元,2012,5,光刻技术,新材料,工艺误差,新结构,工艺集成,芯片制造技术中的五大技术挑战,6,技术挑战,-1:,精密图形转换,?,如何用,193,纳米波长光源形成,65-20,纳米特征长度的图形,?,1.,光学修正,(OPC),相移掩膜,(Phase Shift Mask)2.,浸没式光刻,(Immersion Litho)3.,多重曝光和刻蚀,(Multiple Patterning),7,光刻技术的瓶颈三因素,Phase,Shift,Mask,Off-axis illumination,.,8,光学修正技术使得图形比波长短,光掩模,图形,图形,光掩模,9,Design Rule of Critical Layers,Contact PL Pitch,Fin,193nm Happy Days,193nm,光刻的瓶颈,193,纳米光刻技术支撑,CMOS,发展,65-14nm,10,新材料在,CMOS,中的应用,本世纪来,:,47,种新材料进入,集成电路制造,.,共计,64,种材料,.,12,5,47,技术挑战,-2:,新材料新工艺,11,新材料技术带来的器件性能提高,0.13um,90nm 65nm 45nm 32nm,12,产品技术杀手,:,工艺随机误差,技术挑战,-3:,工艺误差,DFM,：研究工艺误差带来的器件产品性能变化，并提出解决方案。,APC:,及时发现工艺异常,.,13,Direct impact:,SRAM yield,Circuit performance and design margin,Indirect impact:,Reliability,Mobility,Manufacturing control,挑战,：在,低,电压下获得,高,电流和,少,泄漏,即在低电源电压情况下（低电压可以获得好的功耗指标），要设法获得更大的驱动能力和更小的晶体管延时（提高性能）。显然，在传统的体硅平面器件上，已很难实现上述要求,。,栅泄漏电流,寄生电阻,短沟效应,迁移率退化,波动性,动态功耗,驱动能力：,I,DSat,=,C,g,v,inj,C,g,(,V,dd,-,V,t,),eff,功耗：,P,=,C,g,V,dd,2,f,+,I,leakage,V,dd,速度：,g,=,C,g,V,dd,/,I,DSat,来源：北京大学黎明研究员,体硅平面工艺似乎走到尽头,?,技术挑战,-4:,新结构,14,3,维晶体管,FinFET,功函数,高,K,材料,源漏电阻,电路模型,沟道材料,接触电阻,新器件的设计,问题,新一代,FinFET,器件的结构优化,应力分布模拟、迁移率提取、输运机制、可靠性与涨落特性,器件结构参数和工艺参数对电路性能的影响,可制造性,问题,栅泄漏电流，功函数调节，源漏串联电阻及接触电阻等关键问题,材料体系与工艺技术的稳定性可靠性问题,大生产平台上,工艺集成,问题,自对准多次曝光技术，纳米级,Fin,和,Gate,的光刻和刻蚀，节距的缩小带来的原子水平的间隙填充，低介电常数侧墙，超低,K,铜互连等。,15,800,1000,1400,65nm,45nm,20nm,65-14,纳米,CMOS,工艺流程复杂度,技术挑战,-5:,工艺集成技术,每一代新技术需要约,20%,以上的工艺设备添置和更新,几乎每步工艺需要实验,关键工艺需要数百次,1200,32nm,1600,14nm,16,Outline,Major Technology Challenges,SMICs Technology R&D Strategies and Plans,Continue to build&enhance high quality and innovative R&D at SMIC,Place significant focus on leading-edge differentiation technologies,Strengthen R&D on advanced CMOS technology,Enrich design IP to actively support design houses for faster TTM,Actively drive the growth in domestic IC industry chain,3.Concluding Remarks,17,HV,0.13m,0.16m,0.20m,0.25m,0.35m,LCOS,0.13m,0.18m,0.25m,0.35m,MEMS,0.13m,0.18m,14nm,28nm,RF/MS,28nm,40nm,55nm,65nm,90nm,0.13m,0.18m,SOC platforms,Flash,(ETOX),38nm,45nm,65nm,90nm,0.13m,0.18m,0.25m,e-Flash,55nm,90nm,0.11m,0.13m,0.18m,Imager,55nm BSI,90nm FSI/BSI,0.11m BSI,0.13m FSI,0.15m FSI,0.18m FSI,EEPROM,0.11m,0.13m,0.18m,0.35m,40nm,65/55nm,90nm,0.11m,0.13m,0.15m,0.18m,0.25m,0.35m,Logic,Baseline,PMIC,0.13m,0.18m,0.35m,SOC platforms,SMICs Two-Pronged Technology Strategy,18,28nm,Readiness and MPW,Milestones,1,st,SMIC,28nm MPW,Dec/2013,MPW,28PS&28HK,V0.5 V0.5,Nov/2013 Jan/2014,PDK,28PS&28HK,Q4/2014-Q1/2015,Process,Qualification,28PS&28HK,Dec/2013,Process,Freeze,4Q13,On Time Delivery!,Y14 NTO Year,Y14,MPW,4 Shuttles:28PS,28HK,Apr,Jun,Aug,Dec,28nm,Milestone,19,MTE Device Structure,Device Structure:2x gate density,Advantages,50%reduction in transistor pitch from 0.79um to0.39um by SA/SB shrunk.,1/3 parasitic S/D junction capacitance compare to conventional structure.,Actual Performance,Standard Cell library:37%area shrunk in pared to 13LL,SRAM:50%bitcell size(1.05um2)vs 13LL(2.03um2)with 2pA/cell Istdby,SRAM:Smallest bitcell(0.74um2)10M yield 67%,GT,CT,N+,N+,PW,0.13,0.04,0.16,0.13,Poly2,0.13 MTE,GT,CT,CT,N+,N+,PW,0.06,0.11,0.16,0.13,0.13 BL,20,MTE Merits High Performance,Parameter,unit,013MTE*,013LL,MTE vs.LL,W,um,100,100,N/A,SA/SA,um,0.13,0.38,N/A,Cj0_total_,n15,fF,14.05,28.994,-51.5%,Cgd0_total_,n15,fF,42,38.9,8.0%,S/D_CV_total_,n15,fF,56.05,67.894,-17.4%,Cj0_total_,p15,fF,11.18,47.31,-76.4%,Cgd0_total_,p15,fF,43.9,36.1,21.6%,S/D_CV_total_,p15,fF,55.08,83.41,-34.0%,Junction capacitor table from SPICE model,As high as,70%,reduction in S/D parasitic capacitance was obtained in latest lot.,Device fine tuning needed to further reduce parasitic junction capacitance.,GT,CT,N+,N+,PW,0.13,Cj,=,=,Cgd,0.13 MTE,21,22,Driving Technology R&D with Innovation,Source:Corp.Legal,data as of July.29,2014,Patents filed:9,088 total,Patents granted:4,174 total,Issued patents,Filed patents,SMIC is amongst the,Top 5 companies in China,in,numbers of patents granted,16,纳米节点关键技术,FinFET,世界前十一名,中国第,1,位,22,Grow,Competitive Portfolio,for Mobile Internet,Current focuses:28nm,20nm,16nm,14nm,3D IC,IP design,MEMS and new memory,3G Production,Technologies,4G R&D Completed,Source:SMIC dada,23,SMICs Technology Portfolio,In Production,Major Focus(close to or in early production),Future Plan,20/14nm,28nm,38nm,40/45nm,55nm,65nm,90nm,0.11m,0.13m,0.15/0.153,m,0.18m,0.25m,0.35m,Power Mgmt,MCU,Image&Display,Mobile Computing,Digital Home,Wireline Comm.,Wireless,Connectivity,NOR/NAND/,Memory,Smart Card,24,中芯国际多元差异化器件和互连与,3D,系统集成技术全貌,PMIC,RF,CMOS,CIS,Emb-,NVM,Mass,Storage,NVM,Logic,0.35um,0.25um,0.18/0.15um,0.13/0.11um,90nm,65/55nm,45/40nm,28nm,20/14nm,Al,BEOL,Cu LK,&ELK,TSI,SiP,CMOS,e-TSV,I/O,多元差异化核心器件及芯片技术,TSV,转接板及,2.5D,系统集成,先进逻辑,互连及,3D,系统集成,2D,片上互连,RF,SOI,CMOS,MEMS,3D,系统集成,Wide I/O,3D,WtW,Stack,3D,芯片,25,中芯国际,TSV,与,3D,芯片及系统集成技术产业化进程表,产业化,基于,TSV,的,2.1/2.5D,系统集成,基于,TSV,的,3D,芯片级,系统芯片,集成,基于,TSV,的,3D,晶圆级,系统芯片,堆叠集成,TSV BS GRD,HP RF&PMIC,客户设计,客户设计,客户设计,工艺定型,工艺定型,工艺定型,工艺定型,客户设计,构架及模块技术开发,构架及模块技术开发,工艺定型,客户设计,工艺定型,客户设计,构架及模块技术开发,工艺定型,客户设计,High density I/O,WL Fan-Out,WL integration,Low cost,Low profile,6514nmLG,6520nm NVM,HP MCU,KGD resolved,Low cost,国家,02,产业化项目,26,FinFET Features demo-ed:,3D fin based,All-last RMG,Local interconnect MOL,64nm BEOL metal pitch with double patterning,Functional transistors with excellent electrostatic performance!,Features in working,pFET epi SiGe on fin,nFET epi Si/SiC on fin,Self-aligned local inter-connect contact(SAC),ID(A/um),VG(V,),14nm,先导技术研究进展：,FinFET,工艺结果,Source:SMIC dada,27,Gate Poly,STI,Fin,Raised EPI,Devices Beyond FinFET,Gate-All-Around Nanowire FET,Bangsaruntip,IEDM 2009,TFET(Tunnel FET)Villalon,VLSI 2012,for ultra-low-power application,High-mobility Channel FET,Yokoyama,VLSI 2011,High-mobility,Channel FinFET,Radosavljevic,IEDM 2010,28,Continue to Strengthen IP Investments,SMIC Historical Third,Party IP Investment,All actual engaged or forecast IP investment are“Booking”based,Continuously,focusing on investing advanced technology,Driving 28nm IP Investment to meet customers needs,Single user-friendly interface to access all technical information,with accuracy and consistency,1,1.5X,2.2X,29,1st Time,Success,Production,Yield,Production,Stability,Delivery,Cycle,Lowest,Cost,Customer Satisfaction,Defect,Density,Excellence,Manufacturing Excellence,Quality,Service,Technology,Customer Oriented,30,Design house,Equipment,Foundry,Material,Strong Partnership with Domestic IC Industry Chain,31,Front-end,Middle-end,Back-end,12”Bumping JV with JCETBuilding Chinas Domestic IC Supply Chain,Will strengthen the co-operation in the 3D wafer level packaging field,SMICs advanced,40nm&28nm,process technology,12,Bumping,production line jointly built with JCET,JCETs,Package,production line,at nearby Middle-end facility,32,Collaboration with Universities and Research Institutes,Original Innovation,原始创新,New architecture New material&process,新结构,新材料,新工艺,Scientist lead innovation,充分发挥科研院所,/,高校的创新精神,Advanced Technology,Marketing oriented,企业引导、瞄准市场,Academic Effect,具有较高学术影响,Application adopted,先导性成果争取获得企业应用,Pre-Manufacture Technology,Know-How Dominated,技术细节为主体,Efficiency and cost,快、赶、省，企业发展路线图,Theoretic support from Univ.,科研院所,/,高校提供理论支持,Manufacture Technology,Innovation Driven,Market Driven,14-10nm,28-20nm,7nm,33,Outline,Major Technology Challenges,SMICs Technology R&D Strategies and Plans,Continue to build&enhance high quality and innovative R&D at SMIC,Place significant focus on leading-edge differentiation technologies,Strengthen R&D on advanced CMOS technology,Enrich design IP to actively support design houses for faster TTM,Actively drive the growth in domestic IC industry chain,3.Concluding Remarks,34,我国的集成电芯片制造距离世界先进水平技术差距,3,年。,工艺技术发展中的五大挑战（光刻、材料、随机误差、结构、工艺集成），其中光刻瓶颈尤为明显。,先进工艺步伐趋缓，但是世界龙头在,20-14,纳米（及以下）产业化技术发展加快。,中芯国际发挥中国市场的主场优势，保持技术发展步伐，实行差异化发展。,设计,IP,的建设正在得到更多的重视。,产业链需要加强产业联盟的建设,促进产学研协同创新,。,小 结,35,Thank You,谢谢,Diversified Technologies for Various Applications,Power,Management,PMIC,PMU,Discrete Power,Wire-line Communication,Flash Controller,USB,Bridge IC,TCON,Audio,Video,Image&Display,Mobile Phone CIS,DSC/DV/DPF,NB/PCCAM,MCU,Touchpad controller,MCU,Smart Card,Financial Card,Bank Card,ID Card Transportation Card,ePassport,etc,Wireless,Connectivity,Wi-Fi,Bluetooth,GPS,AM/FM,NFC,etc,Mobile,Computing,Mobile Phone,Tablets,Application Processors,Baseband,SoC,Memory,NOR Flash,NAND Flash,eNVM,Digital Home,TV,Set-Top Box,Game Consoles,Projector,37,14,纳米以下的研究发展趋势,(863,项目,),传统平面晶体管,三栅,FinFET,22nm,FinFET,16/14nm,FinFET,10nm,FinFET?FDSOI?,7nm,X device?,技术细节未明,技术方案不确定,2012,2014,2016,2018,单栅控制,短沟道效应,涨落,迁移率退化,多栅控制,全耗尽沟道,3D,集成度,38,Integrity,Capability,Excellence,CSR,Building Customers Trusts&Success,Building Long Term Partnerships for Mutual Success,Protect Customers,Interests&IPs,Steady Growth with Confidence&Competence,Building Technology Roadmap&Service Offerings,Discipline&Manufacturing Excellence,Innovation,Quality&Safety,Your Trusted Foundry Partner in China,Achievements in EHS,Environmental Protections,Social Responsibility,Charity Program on,Liver Transplant,39,3D,结构器件：,14,纳米,FinFET,Gate Poly,STI,Fin,Raised EPI,用,3D,晶体管替代平面晶体管,Source:SMIC dada,40,