SK培训资料单片机介绍.ppt

Title Goes Here,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,TM,Confidential and Proprietary,*,TM,2014 Freescale Semiconductor,Inc.|,Confidential and Proprietary,www.F,Title Goes Here,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,TM,Confidential and Proprietary,*,S32K培训资料单片机介绍,Agenda,KFA series,KFA family architecture,Safety,Performance,Clocking,Power Management,ADC&triggering subsystem,Compatibility,Communication peripherals,FlexIO,Software and Enablement,Summary,KFA Series-Introduction,Key Hardware Features,High performance ARM Cortex architecture,Low power 30%better than todays benchmark,Scalability from 16KB to 2MB embedded flash,FlexCAN with CAN FD option,FlexIO for configurable number of LIN,SPI,I2C,Targeting ASIL-B applications,Security,Key Software Features,KDS(Kinetis Design Studio),Autosar MCAL and,OS,Non-autosar Low-Level Drivers,Model-based design support,Extensive 3,rd,party offering,General Purpose MCU Roadmap,2014,2015,2016,2017,Entry,90nm,First,Sample Date,(left edge),Product,Qualification,(right edge),Proposal,Planning,Production or,Execution,180nm,Last Updated 10SEP14,2018,KFA 512,M4 up to 120MHz,KEA64,M0+,40MHz,KEA8,M0+,48MHz,Mainstream,High,performance,KEA128 M0+48MHz,64-128kB,LIN,CAN,64-80pin,16-64kB,LIN,32-64pin,8kB,LIN,16-24pin,256-512kB,FlexIO,CAN-FD,48-144pin,64-128kB,LIN,CAN,32-64pin,KFA 1M,M4 up to 150MHz,768kB-1M,FlexIO,CAN-FD,100-176pin,KFA 2M,M4/M0+up to 180MHz,1.5M-2M,FlexIO,CAN-FD,Ethernet,Security 100-176pin,KGA 128,M0+,64MHz,16-32kB,LIN,20-48pin,KGA 32,M0+,48MHz,High temp,(AEC Grade 0),Cortex,M4/M0+,KFA512 Block Diagram,Preliminary and subject to change,Communications I/O System,Peripheral Bus,SWD,JTAG,Debugger,Debug,RAM,Up to,64KB,System,Peripheral,Bridge,Flash,Up To,512K,NVIC,Cortex M4,80/120MHz,FPU,DSP,MPU,EEPROM,4KB,2x16ch,12bit,Dual ADC,2,ACMP,Flex IO peripheral,16ch/64ch,eDMA,WDT,EWM,PMC,2.7-5.5V,POR,FLL Clk Mult,LVD,Ext Osc,(4-40MHz),Int R/C OSC,(48MHz 1%),Int LP Osc,(128KHz),SCG,High performance,ARM Cortex M4 up to 120MHz w FPU,eDMA from Qorivva family,Software Friendly Architecture,High RAM,to Flash ratio,Independent CPU and periph clocking,48MHz IRC no PLL init required in LP,registers,maintained,in,all modes,Programmable triggers for ADC,no sw delay counters or extra interrupts,Functional safety,ISO26262 support for ASIL,B or higher,MPU,ECC on Flash/Dataflash and RAM,Independent,internal OSC for Watchdog,Diversity between ADC and ACMP,Diversity between SPI/SCI and FlexIO,Core self test,libraries,Scalable LVD protection,Low power,Low leakage technology,Multiple VLP modes and IRC combos,Wake-up on analog thresholds,4x8ch,16-Bit,FlexTimer,2,I2C,3,SPI,4,SCI,(LIN),2,PDB,3,FlexCAN,w FD,1,PIT,Open-,Drain IO,KBI,GPIO,Digital,Components,5V Analogue,Components,MCU Core and Memories,1,API,RTC,Operating CharacteristicsI/Os,Voltage range:2.7 to 5.5 V,64/100pin compatible within Family,Temperature(ambient):-40 to 125COpen-drain for 3.3V and hi-drive pins to save,BOM,Powered ESD protection,Safety,MCU HW,Know Your Safety System Context,How to make the system safe?,Optimal partitioning between Safety System HW&SW measures scaled to complexity of vehicle safety function,Simple,Safety,Functions are,implemented,on a high abstraction level(vehicle&ECU),Complex*,Safety,Functions are,implemented using a,combination of low(MCU HW)and high abstraction level(vehicle&ECU),Complex,Safety,Function,(e.g.EPS),Simple,Safety,Function,(e.g.Airbag),EPS,ESP,Engine Management HEV,ASIL D,target,ASIL A,target,ASIL B,target,ASIL C,target,*,A,Complex,Safety,Function(vehicle level)here refers to the combination of a,high,computational,demand for the application combined with a,short control cycle,.,Safety System HW&SW,Airbag,Body,DIS,RADAR and Vision based ADAS,MCU HW,The Solution,Offering,products scaled,to vehicle,safety function complexity,from across the Freescale product portfolio,ISO 26262,developed products cover the complete range,Standard,products,cover systems with simple safety functions,Where we enable the customer to do the Qualification,testing and analysis to prove that our component is suitable for the purpose of his safety concept.,Covering the,whole,range,efficiently,ASIL D,target,Complex,Safety,Function,Simple,Safety,Function,ASIL A,target,ASIL B,target,ASIL C,target,EPS,ESP,Engine Management HEV,Safety System HW&SW,Airbag,Body,DIS,RADAR and Vision based ADAS,SafeAssure,SEooC HW,Developed for,ISO 26262,(10.9 Safety Element out of Context),SafeAssure,Standard HW,Enabled for,ISO 26262,(8.13 Qualification of Hardware Components),Full ASIL safety tracking KFA family sample extract,Single Point Fault Metric,RAM ECC,Flash ECC,Undervoltage monitoring,Clock Monitoring,Temporal protection Software Watch dog,SMPU,execution control,Register protection,CRC,Individual Peripheral safety support measures,ECC Error Handling,Single bits:Flash,handled/repaired automatically,Single bits:SRAM,Error address capturing,Interrupt generated,Customer s/w can,handle,Double bits:Code Flash,Machine Exception-software decision,If second double bit error-force h/w reset,Double bits:,Data Flash&SRAM,Machine Exception-software decision,Customer s/w can handle,Functional Safety,Diversity of safety levels,LPSPI or LPSCI v FlexIO,Create completely alternate SPI/SCI communication paths,Ultra high parallelisation of data integrity,Analogue input monitoring,Analogue measuring via completely independent system resources,Independent references,independent peripherals,Class leading monitoring protection schemes,Safety Support(Cyclic Redundancy Check-CRC),The cyclic redundancy check(CRC)module generates 16/32-bit CRC code for error,detection,The CRC module provides a programmable polynomial,seed and other parameters,required to implement a 16-bit or 32-bit CRC standard.,The 16/32-bit code is calculated for 32 bits of data at a time.,CRC Engine,CRC Data,Polynomial,Example:Using DMA for CRC Calculation,eDMA,DMA Request Mux,LPUARTs,LPSPIs,I,2,Cs,FTMs,ADCs,HSCMPs,FlexIO,PDB,GPIOs,63 DMA,Requests,SCG,SIM,clock,NVIC,error int,DMA CH0 int,DMA CH1 int,DMA CH16 int,DMA Mux,SPIs,DMA Mux,CRC,Source(Flash),Destination(CRC),Safety Support -Watchdog Timer(WDOG),Safety Support -External Watchdog Monitor(EWM),Performance,KFA512 High Level Architecture,Operating profile flash reliability,The below profile is within the targeted development mission profile for qualification and the targeted data retention spec for KFA.,Suitable for even the most stringent automotive lighting application.,Assume 8000hrs operating(1 year):,2100hrs 125C,3000 105C,1500 40C,1000 25C,400 0C,Non-operating(14 years):,-122000hrs 25C average/vehicle stopped,DMA Mux Allocations,Clocking,High Level Clocking Architecture,Clock sources,FIRC:48MHz 60MHz,1%accuracy after trimming,across PVT,300uA consumption,SIRC:8MHz,10%accuracy,20uA consumption,LPO:128KHz,-RUN,-,STOP,-,RUN-VLPS approach,Use API to wake up periodically,Clock core and ADC0 from,8,MHz,S,IRC,Use STOP,state,during,the sensor,stabilization,period,Return,to,VLPS unless,pre-defined conditions exceeded,2ms,10ms,20,m,A,35mA,20mA,Run Current range,RUN,from RAM,45,m,s,1,m,s,10,m,s,65,m,s,Run from RAM&read sensor,45,m,s,10,m,s,10,m,s,Run from RAM&enable sensor,45,m,s,1,m,s,10,m,s,56,m,s,VLPS Current,300,m,A,STOP,VLPS,ADC&Triggering Subsystem,KFA512 ADC Configuration,ADC0,ADC1(12Bit),Channel configuration,16 Standard Internal Channels,3 Special Internal Channels,Conversion Time=1us(incl sample),ENOB=10.5 bits,TUE=+/-6bits,700uA 1us conversion,ADC1,12Bit,16 channels,Bandgap,Ana Supply,VrefH,PMC,ADC0,12Bit,16 channels,Bandgap,Ana Supply,VrefH,ADC Triggering Scheme Overview,The KFA family supports two types of ADC triggering:,ADC software trigger,ADC hardware trigger,Using PDB,Using LPIT,Using TRGMUX,ADC Conversion using DMA Configuration,SAR ADC,HW Trigger,Channel,Trigger,DMA request,DMA 0,Buffer,(results),Result,Conversion complete,DMA request,DMA 1,DMA link,Buffer,(channels),DMA interrupt,BCR=0,Trigger,starts ADC conversion,ADC,conversion complete flag starts the DMA 0,DMA,0 copies the ADC result to buffer and generates a link to DMA1,DMA 1 copies next ADC channel ID from buffer to ADC register,When BCR is 0(DMA done flag),DMA interrupt is generated,ADC Hardware Trigger Method 1:Using PDB,PDB is the suggested ADC triggering module.PDB0 is intended to function with ADC0,so as PDB1-ADC1 and PDB2-ADC2.There are dedicated interconnection between the pair of PDB and ADC.,ADC Hardware Trigger Method 2:Using LPIT,LPIT is another optional ADC triggering module.Different with PDB,LPIT can be used to trigger any of the three ADCs through TRGMUX.But LPIT only supports 4 independent timer channels,which leads to a limitation of only 4 pre-triggers for ADC.The 4 LPIT channels can be used to flexibly trigger any ADC.For example:,4 ch to trigger 13 ADCs at same time,each ADC with 4 result registers,4 ch to trigger 2 ADCs independently,each ADC with 2 result registers,-.,Note:,LPIT doesnt support ADC_COCO feedback,it needs software to correctly control the ADC trigger timing setting.,Note:,Following diagram only shows PDB0-ADC0,its the same with PDB1-ADC1 and PDB2-ADC2.,ADC Hardware Trigger Method 3:Direct trigger,For direct ADC trigger(not using PDB or LPIT),the ADC supports up to 4 ADHWTn.,ADC,TRGMUX,Logic“0”-VSS,Trigger source A,SW pre-trig,OR,0,0,0,SW pre-trig,ADHWT,ADHWTS0,ADHWTS1,Trigger Multiplexing(TRGMUX),Trigger Multiplexing(TRGMUX continued),FlexTimer Module,FTM source clock is selectable with prescaler divide-by 1,2,4,8,16,32,64,or 128 from Busclock,FTM has a 16-bit counter,2 up to 8 channels,(inputs/outputs),The,counting,can be,up,or,up-down,Each channel can be configured for input capture,output compare,or PWM generation,Input filter can be selected for some channels,New,combined mode to generate a PWM signal,(with independent control of both edges of PWM signal),Complementary outputs,include the deadtime insertion,Software control of PWM outputs,Up to,4 fault inputs,for global fault control,The polarity of each channel is configurable,The generation of an interrupt per channel input capture/compare,counter overflow,at fault condition,Synchronized loading of write buffered FTM registers,Write protection for critical registers,Backwards compatible with TPM on other Freescale MCUs,Dual edge capture for pulse and period width measurement,Quadrature decoder with input filters,relative position counting and interrupt on,Position count or capture of position count on external event,Compatibility,KEA to KFA Compatibility,The KFA series will be 100%compatible within the KFA family,Eg KFA512 lqfp 100 is identical to the KFA1M lqfp100,The KFA series will be pin compatible with the KEA range,with the following exceptions:,The KFAxxx 64 pin device will have the VrefH bonded out on pin 9.On the KEA devices,pin 9 was VrefL,Rationale for change:VrefH offers more useful application functionality,The KFAxxx devices will offer increased functionality,hence multiple new alternate levels of multiplexing will be available,The 100 pin device is new to the family,hence there is no compatibility legacy requirements,For clarity,the 8 high drive pins on the KEA will also be present in the same positions on the KFA.,Compatible 64lqfp pin-out to the KEA series,Communication peripherals,Low Power SPI(LPSPI),The LPSPI is a low power Serial Peripheral Interface(SPI)module that supports an efficient interface to an SPI bus as a master and/or a slave.The LPSPI can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses.,Main features:,Command/transmit FIFO of 4 words.,Receive FIFO of 4 words.,Host request input can be used to control the start time of an SPI bus transfer.,Low Power IIC(LPI2C),The LPI2C is a low power Inter-Integrated Circuit(I2C)module that supports an efficient interface to an I2C bus as a master and/or a slave.The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses.,The LPI2C implements logic support for standard-mode,fast-mode and fast-mode plus modes of operation.It also supports high speed mode,supporting either complementary drive or current source pullup depending on what pin is used.The LPI2C module also complies with the System,Management Bus(SMBus)Specification,version 2.,LPUART,Features of the LPUART module include:,Full-duplex,standard non-return-to-zero(NRZ)format,Programmable baud rates(13-bit modulo divider)with configurable oversampling ratio from 4x to 32x,Transmit and receive baud rate can operate asynchronous to the bus clock:,Baud rate can be configured independently of the bus clock frequency,Supports operation in Stop modes,Interrupt,DMA or polled operation,Hardware parity generation and checking,Programmable 8-bit,9-bit or 10-bit character length,Programmable 1-bit or 2-bit stop bits,Independent FIFO structure for transmit and receive,Hardware flow control support for request to send(RTS)and clear to send(CTS),signals,Three receiver wakeup methods(Idle line,Address mark,Receive data),Automatic address matching to reduce ISR overhead,:,Address mark matching,Idle line address matching,Address match start,address match end,Optional 13-bit break character generation/11-bit break character detection,Configurable idle length detection supporting 1,2,4,8,16,32,64 or 128 idle,characters,Selectable transmitter output and receiver input polarity,FlexCAN3 Architecture,Full Implementation of the CAN protocol specification,Version 2.0B,Flexible Message Buffers(16)of zero to eight bytes data length,MB each configurable as Rx or Tx,all supporting standard and extended messages,Individual Rx Mask Registers per Message Buffer,Full featured Rx FIFO with storage capacity for 6 frames and internal pointer handling,DMA request for Rx FIFO,Powerful Rx FIFO ID filtering,capable of matching incoming IDs against either 8 extended,16,standard or 32 partial(8 bits)IDs,with individual masking capability,Programmable clock source to the CAN Protocol Interface,either bus clock or crystal oscillator,Programmable transmission priority scheme:lowest ID,lowest buffer number or highest priority,Time Stamp based on 16-bit free-running timer,CAN FD support added to cut2.0,KFA512 FlexCAN3 enhancements,Enhanced Feature,DMA Request added to FlexCAN RxFIFO,Allows CPU longer time to service the received CAN messages.With the DMA connected the depth of the FIFO can be kept small,RxFIFO,Control,Write_Pointer,Read_Pointer,0,1,2,3,4,5,RxFIFO,System,DMA,DMA Req,DMA Ack,System,RAM,CAN FD Support,CAN FD,stands for,CAN with Flexible Data-Rate,CAN FD is a variant of CAN proposed by Bosch to:,Increase the bit rate of the data portion of a CAN message(Up to 1-8Mbps),Increase the number of data bytes that can be sent in a single CAN message to up to 64 bytes(,vs,standard 8 bytes),CAN F