数字电路课程设计数字钟大学论文.doc

大连理工大学本科实验报告

题目：数字钟

课程名称： 数字电路课程设计
学院（系）： 电子信息与电气工程学部
专 业： 电气工程及其自动化
班 级：
学生姓名：
学 号：
完成日期：
成 绩：

2017 年 1 月 7 日
题目：数字钟
1 设计要求
1、设计一个数字钟，能够显示当前时间，分别用6个数码管显示小时、分钟、秒钟的时间，秒针的计数频率为1Hz，可由系统脉冲分频得到。
2、在整点进行提示，可通过LED闪烁实现，闪烁频率及花型可自己设计。
3、能够调整小时和分钟的时间，调整的形式为通过按键进行累加。
4、具有闹钟功能，闹钟时间可以任意设定（设定的形式同样为通过按键累加），并且在设定的时间能够进行提示，提示同样可以由LED闪烁实现。

2 设计分析及系统方案设计
2.1 系统状态转换
因为数字钟成正常显示时间、闹钟、校时、秒表四个状态，所以可以选用两个开关来对其状态进行控制，当开关分别为00，01，10，11四种状态时，对应显示时间、修改时间、闹钟、秒表四种状态。
显示时间
修改时间，使用两个开关分别对位和数字更改
闹钟，使用两个开关分别对位和数字进行更改
秒钟，使用一个开关控制秒钟的开始和关闭
四个状态
00
01
10
11

2.2 时钟信号的建立
该多功能数字钟系统需要两个时钟信号，分别为1Hz的信号为数字钟提供秒信号以及200Hz的检查信号。本设计选用50MHz信号，分别将其通过模25000000计数器和模125000计数器从而得到1Hz及200Hz信号。
2.3 功能分析及其设计
2.3.1时间显示功能
当两个开关都处于低电平状态时，正常显示
2.3.2 修改时间
当sw1处于低电平状态，sw0处于高电平状态，进入当前时间修改功能。通过按键key0分别选择修改时、分或秒，通过按键key1对选择修改的时间进行+1操作。
2.3.3 闹钟
当sw1出于高电平状态，sw0出于低电平状态，进入闹铃功能。通过按键key0分别选择改变时、分或秒，通过按键key2对选择改变的时间进行+1操作，当数字钟到当前时间，LEDG0发光。
2.3.4 秒表
当sw1及sw0都处于高电平状态，进入秒表功能。通过按键key0进行秒表计时的开始及暂停，通过按键key3对秒表进行清零。
3系统以及模块硬件电路设计
3.1 硬件原理图

图3.1 系统示意图

图3.2 按键电路

图3.3 状态选择按键

图3.4 闹钟使用的led

3.2 管脚定义
程序代码
引 脚
功能作用
clk
PIN_N2
提供50MHz的时钟信号
s1
PIN_N25
选择功能状态
s2
PIN_G26
选择功能状态
k1
PIN_G26
切换改变时间功能的时、分、秒；切换闹钟功能设置闹钟时间的时、分、秒；秒表功能的开始与暂停
k2
PIN_N23
改变时间功能的+1
k3
PIN_P23
闹钟功能设置闹钟时间的+1
k4
PIN_W26
秒表功能的清零
LED
PIN_AE22
闹钟时间到来时指示
dclkh1[0]
PIN_N9
连接HEX7，
显示时高位
dclkh1[1]
PIN_P9
dclkh1[2]
PIN_L7
dclkh1[3]
PIN_L6
dclkh1[4]
PIN_L9
dclkh1[5]
PIN_L2
dclkh1[6]
PIN_L3
dclkh2[0]
PIN_M4
连接HEX6，
显示时低位

dclkh2[1]
PIN_M5
dclkh2[2]
PIN_M3
dclkh2[3]
PIN_M2
dclkh2[4]
PIN_P3
dclkh2[5]
PIN_P4
dclkh2[6]
PIN_R2
dclkm1[0]
PIN_R3
连接HEX5，
显示分高位

dclkm1[1]
PIN_R4
dclkm1[2]
PIN_R5
dclkm1[3]
PIN_T9
dclkm1[4]
PIN_P7
dclkm1[5]
PIN_P6
dclkm1[6]
PIN_T2
dclkm2[0]
PIN_T3
连接HEX4，
显示分低位
dclkm2[1]
PIN_R6
dclkm2[2]
PIN_R7
dclkm2[3]
PIN_T4
dclkm2[4]
PIN_U2
dclkm2[5]
PIN_U1
dclkm2[6]
PIN_U9
dclks1[0]
PIN_W24
连接HEX3，
显示秒高位

dclks1[1]
PIN_U22
dclks1[2]
PIN_Y25
dclks1[3]
PIN_Y26
dclks1[4]
PIN_AA26
dclks1[5]
PIN_AA25
dclks1[6]
PIN_Y23
dclks2[0]
PIN_Y24
连接HEX2，
显示秒低位

dclks2[1]
PIN_AB25
dclks2[2]
PIN_AB26
dclks2[3]
PIN_AC26
dclks2[4]
PIN_AC25
dclks2[5]
PIN_V22
dclks2[6]
PIN_AB23

4 系统的Verilog设计
//顶层模块
module clock(clk,dclks1,dclks2,dclkm1,dclkm2,dclkh1,dclkh2,s,h,state,s1,s2,k1,k2,k3,k4,LED);

input clk; //声明输入端口，连接50M晶振
input s1,s2; //声明输入端口，控制功能转换
input k1,k2,k3,k4; //声明输入端口，连接按键，对功能内部进行设置
output LED; //声明输出端口，连接LED闹钟指示
output s,h;//声明输出端口，为各功能提供秒信号
output state;//声明输出端口，表示当前状态
output [6:0] dclks1,dclks2,dclkm1,dclkm2,dclkh1,dclkh2;
//声明输出端口，连接数码管，

reg [31:0] c,e;
reg s,h;
reg b;
reg [1:0] state;
wire [7:0] cs0,cm0,ch0,cs1,cm1,ch1,cs2,cm2,ch2,cs3,cm3,ch3;//分别连接四个状态的时分秒
reg [7:0] clks,clkm,clkh,clks1,clkm1,clkh1;
wire [6:0] dclks1,dclks2,dclkm1,dclkm2,dclkh1,dclkh2;
reg [1:0] k,a,d;
reg LED;
reg clkf;

always@(negedge k1) //检测k1
begin
if(state==2'b01)
begin
if(k==2'd2)
k<=2'd0;
else
k<=k+1'd1;
end
else if(state==2'b10)
begin
if(a==2'd2)
a<=2'd0
else
a<=a+1'd1;
end
else if(state==2'b11)
begin
b<=~b;
end
end

always@(negedge k4)//检测k4
begin
if(state==2'b11)
begin
if(d==1'b1)
d<=1'b0;
else
d<=d+1'b1;
end
end

always@(posedge clkf)//定义状态
begin
case({s1,s2})
2'b00:state=2'd0;
2'b01:state=2'd1;
2'b10:state=2'd2;
2'b11:state=2'd3;
default:state=2'd0;
endcase
end

always@(posedge clk)//提供1Hz信号
begin
if(c==32'd24999999)
begin
s<=~s;
h<=~h;
c<=1'd0;
end
else
c<=c+1'd1;
end

always@(posedge clk)//提供200Hz信号
begin
if(e==32'd125999)
clkf<=~clkf;
else
e<=e+1'b1;
end

always@(posedge clkf)//检验时间是否到设定的闹钟
begin
if(cs2==cs0&&cm2==cm0&&ch2==ch0)
LED<=1'b1;
else
LED<=1'b0;
end

always@(posedge clkf)
begin
if(state==1'b0)
begin
clks<=cs0;
clkm<=cm0;
clkh<=ch0;
end
else if(state==2'd1)
begin
clks1<=cs1;
clkm1<=cm1;
clkh1<=ch1;
clks<=cs0;
clkm<=cm0;
clkh<=ch0;
end
else if(state==2'd2)
begin
clks<=cs2;
clkm<=cm2;
clkh<=ch2;
end
else if(state==2'd3)
begin
clks<=cs3;
clkm<=cm3;
clkh<=ch3;
end
end

de2time u0(.cs0(cs0),.cm0(cm0),.ch0(ch0),.s(s),.state(state),.clkf(clkf),.clks1(clks1),clkm1(clkm1),.clkh1(clkh1));
de2timechange u1(.cs1(cs1),.cm1(cm1),.ch1(ch1),.state(state),.k2(k2),.k(k));
de2alarm u2(.cs2(cs2),.cm2(cm2),.ch2(ch2),.a(a),.k3(k3),.state(state));
de2timer u3(.cs3(cs3),.cm3(cm3),.ch3(ch3),.b(b),.h(h),.clkf(clkf),.d(d));
bdtransform u4(.clks(clks),.clkm(clkm),.clkh(clkh),.dclks1(dclks1),.dclks2(dclks2),.dclkm1(dclkm1),.dclkm2(dclkm2),.dclkh1(dclkh1),.dclkh2(dclkh2),.clkf(clkf));
endmodule
//正常时间显示模块
module de2time(clks1,clkm1,clkh1,s,state,cs0,cm0,ch0,clkf);

input s;
input clkf;
input clks1,clkm1,clkh1;
output cs0,cm0,ch0;
input state;

wire s;
wire clkf;
wire [7:0] clks1,clkm1,clkh1;
wire [1:0] state;
reg [7:0] cs0;
reg [7:0] cm0;
reg [7:0] ch0;

always@(posedge s)
begin
if(state==2'd0||state==2'd2||state==2'd3)
begin
if(cs0==6'b111011)
begin
cs0<=0;
cm0<=cm0+1'b1;
if(cm0==6'b111011)
begin
cm0<=0;
ch0<=ch0+1'b1;
if(ch0==5'b10111)
begin
ch0<=0;
end
else ;
end
else ;
end
else
begin
cs0<=cs0+1'b1;
end
end
else
begin
cs0<=clks1;
cm0<=clkm1;
ch0<=clkh1;
end
end

endmodule

//时间更改模块
module de2timechange(cs1,cm1,ch1,state,k,k2);

input state;
input k;
input k2;
output cs1,cm1,ch1;

wire [1:0] k;
wire k2;
wire [1:0] state;
reg [7:0] cs1;
reg [7:0] cm1;
reg [7:0] ch1;

always@(negedge k2)
begin
if(state==2'b01)
begin
if(k==1'd0)
begin
if(cs1==6'b111011)
cs1<=0;
else
cs1<=cs1+1'b1;
end
else if(k==1'd1)
begin
if(cm1==6'b111011)
cm1<=0;
else
cm1<=cm1+1'b1;
end
else if(k==2'd2)
begin
if(ch1==5'b10111)
ch1<=0;
else
ch1<=ch1+1'b1;
end
end
end

endmodule

//闹钟功能模块
module de2alarm(cs2,cm2,ch2,state,a,k3);

input a;
input k3;
input [1:0] state;
output [7:0] cs2,cm2,ch2;

wire [1:0] a;
wire k3;
wire [1:0] state;
reg [7:0] cs2,cm2,ch2;

always@(negedge k3)
begin
if(state==2'b10)
begin
if(a==1'd0)
begin
if(cs2==6'b111011)
cs2<=0;
else
cs2<=cs2+1'b1;
end
else if(a==1'd1)
begin
if(cm2==6'b111011)
cm2<=0;
else
cm2<=cm2+1'b1;
end
else if(a==2'd2)
begin
if(ch2==5'b10111)
ch2<=0;
else
ch2<=ch2+1'b1;
end
end
end

endmodule

//秒表功能模块
module de2timer(cs3,cm3,ch3,b,h,clkf,d);

input b;
input h;
input d;
input clkf;
output [7:0] cs3,cm3,ch3;

wire b;
wire s;
wire d;
wire clkf;
reg [7:0] cs3,cm3,ch3;

always@(posedge h)
begin
if(d==1'b0)
begin
if(b==1'b1)
begin
if(cs3==6'b111011)
begin
cs3<=0;
cm3<=cm3+1'b1;
if(cm3==6'b111011)
begin
cm3<=0;
ch3<=ch3+1'b1;
if(ch3==5'b10111)
begin
ch3<=0;
end
else ;
end
else ;
end
else
begin
cs3<=cs3+1'b1;
end
end
end
else
cs3<=0;
cm3<=0;
ch3<=0;
end

endmodule

//将2进制转换为数码管输出
module bdtransform(clks,clkm,clkh,dclks1,dclks2,dclkm1,dclkm2,dclkh1,dclkh2,clkf);

input clks,clkm,clkh;
input clkf;
output dclks1,dclks2,dclkm1,dclkm2,dclkh1,dclkh2;

wire [7:0] clks,clkm,clkh;
wire clkf;
reg [6:0] dclks1,dclks2,dclkm1,dclkm2,dclkh1,dclkh2;

always@(clkf)
begin
case(clks)
6'd0:{dclks1,dclks2}=14'b00000010000001;
6'd1:{dclks1,dclks2}=14'b00000011001111;
6'd2:{dclks1,dclks2}=14'b00000010010010;
6'd3:{dclks1,dclks2}=14'b00000010000110;
6'd4:{dclks1,dclks2}=14'b00000011001100;
6'd5:{dclks1,dclks2}=14'b00000010100100;
6'd6:{dclks1,dclks2}=14'b00000010100000;
6'd7:{dclks1,dclks2}=14'b00000010001111;
6'd8:{dclks1,dclks2}=14'b00000010000000;
6'd9:{dclks1,dclks2}=14'b00000010000100;
6'd10:{dclks1,dclks2}=14'b10011110000001;
6'd11:{dclks1,dclks2}=14'b10011111001111;
6'd12{dclks1,dclks2}=14'b10011110010010;
6'd13:{dclks1,dclks2}=14'b10011110000110;
6'd14:{dclks1,dclks2}=14'b10011111001100;
6'd15:{dclks1,dclks2}=14'b10011110100100;
6'd16:{dclks1,dclks2}=14'b10011110100000;
6'd17:{dclks1,dclks2}=14'b10011110001111;
6'd18:{dclks1,dclks2}=14'b10011110000000;
6'd19:{dclks1,dclks2}=14'b10011110000100;
6'd20:{dclks1,dclks2}=14'b00100100000001;
6'd21:{dclks1,dclks2}=14'b00100101001111;
6'd22:{dclks1,dclks2}=14'b00100100010010;
6'd23:{dclks1,dclks2}=14'b00100100000110;
6'd24:{dclks1,dclks2}=14'b00100101001100;
6'd25:{dclks1,dclks2}=14'b00100100100100;
6'd26:{dclks1,dclks2}=14'b00100100100000;
6'd27:{dclks1,dclks2}=14'b00100100001111;
6'd28:{dclks1,dclks2}=14'b00100100000000;
6'd29:{dclks1,dclks2}=14'b00100100000100;
6'd30:{dclks1,dclks2}=14'b00001100000001;
6'd31:{dclks1,dclks2}=14'b00001101001111;
6'd32:{dclks1,dclks2}=14'b00001100010010;
6'd33:{dclks1,dclks2}=14'b00001100000110;
6'd34:{dclks1,dclks2}=14'b00001101001100;
6'd35:{dclks1,dclks2}=14'b00001100100100;
6'd36:{dclks1,dclks2}=14'b00001100100000;
6'd37:{dclks1,dclks2}=14'b00001100001111;
6'd38:{dclks1,dclks2}=14'b00001100000000;
6'd39:{dclks1,dclks2}=14'b00001100000100;
6'd40:{dclks1,dclks2}=14'b10011000000001;
6'd41:{dclks1,dclks2}=14'b10011001001111;
6'd42:{dclks1,dclks2}=14'b10011000010010;
6'd43:{dclks1,dclks2}=14'b10011000000110;
6'd44:{dclks1,dclks2}=14'b10011001001100;
6'd45:{dclks1,dclks2}=14'b10011000100100;
6'd46:{dclks1,dclks2}=14'b10011000100000;
6'd47:{dclks1,dclks2}=14'b10011000001111;
6'd48:{dclks1,dclks2}=14'b10011000000000;
6'd49:{dclks1,dclks2}=14'b10011000000100;
6'd50:{dclks1,dclks2}=14'b01001000000001;
6'd51:{dclks1,dclks2}=14'b01001001001111;
6'd52:{dclks1,dclks2}=14'b01001000010010;
6'd53:{dclks1,dclks2}=14'b01001000000110;

6'd54:{dclks1,dclks2}=14'b01001001001100;
6'd55:{dclks1,dclks2}=14'b01001000100100;
6'd56:{dclks1,dclks2}=14'b01001000100000;
6'd57:{dclks1,dclks2}=14'b01001000001111;
6'd58:{dclks1,dclks2}=14'b01001000000000;
6'd59:{dclks1,dclks2}=14'b01001000000100;
endcase

case(clkm)
6'd0:{dclkm1,dclkm2}=14'b00000010000001;
6'd1:{dclkm1,dclkm2}=14'b00000011001111;
6'd2:{dclkm1,dclkm2}=14'b00000010010010;
6'd3:{dclkm1,dclkm2}=14'b00000010000110;
6'd4:{dclkm1,dclkm2}=14'b00000011001100;
6'd5:{dclkm1,dclkm2}=14'b00000010100100;
6'd6:{dclkm1,dclkm2}=14'b00000010100000;
6'd7:{dclkm1,dclkm2}=14'b00000010001111;
6'd8:{dclkm1,dclkm2}=14'b00000010000000;
6'd9:{dclkm1,dclkm2}=14'b00000010000100;
6'd10:{dclkm1,dclkm2}=14'b10011110000001;
6'd11:{dclkm1,dclkm2}=14'b10011111001111;
6'd12:{dclkm1,dclkm2}=14'b10011110010010;
6'd13:{dclkm1,dclkm2}=14'b10011110000110;
6'd14:{dclkm1,dclkm2}=14'b10011111001100;
6'd15:{dclkm1,dclkm2}=14'b10011110100100;
6'd16:{dclkm1,dclkm2}=14'b10011110100000;
6'd17:{dclkm1,dclkm2}=14'b10011110001111;
6'd18:{dclkm1,dclkm2}=14'b10011110000000;
6'd19:{dclkm1,dclkm2}=14'b10011110000100;
6'd20:{dclkm1,dclkm2}=14'b00100100000001;
6'd21:{dclkm1,dclkm2}=14'b00100101001111;
6'd22:{dclkm1,dclkm2}=14'b00100100010010;
6'd23:{dclkm1,dclkm2}=14'b00100100000110;
6'd24:{dclkm1,dclkm2}=14'b00100101001100;
6'd25:{dclkm1,dclkm2}=14'b00100100100100;
6'd26:{dclkm1,dclkm2}=14'b00100100100000;
6'd27:{dclkm1,dclkm2}=14'b00100100001111;
6'd28:{dclkm1,dclkm2}=14'b00100100000000;
6'd29:{dclkm1,dclkm2}=14'b00100100000100;
6'd30:{dclkm1,dclkm2}=14'b00001100000001;
6'd31:{dclkm1,dclkm2}=14'b00001101001111;
6'd32:{dclkm1,dclkm2}=14'b00001100010010;
6'd33:{dclkm1,dclkm2}=14'b00001100000110;
6'd34:{dclkm1,dclkm2}=14'b00001101001100;
6'd35:{dclkm1,dclkm2}=14'b00001100100100;
6'd36:{dclkm1,dclkm2}=14'b00001100100000;
6'd37:{dclkm1,dclkm2}=14'b00001100001111;
6'd38:{dclkm1,dclkm2}=14'b00001100000000;
6'd39:{dclkm1,dclkm2}=14'b00001100000100;
6'd40:{dclkm1,dclkm2}=14'b10011000000001;
6'd41:{dclkm1,dclkm2}=14'b10011001001111;
6'd42:{dclkm1,dclkm2}=14'b10011000010010;
6'd43:{dclkm1,dclkm2}=14'b10011000000110;
6'd44:{dclkm1,dclkm2}=14'b10011001001100;
6'd45:{dclkm1,dclkm2}=14'b10011000100100;
6'd46:{dclkm1,dclkm2}=14'b10011000100000;
6'd47:{dclkm1,dclkm2}=14'b10011000001111;
6'd48:{dclkm1,dclkm2}=14'b10011000000000;
6'd49:{dclkm1,dclkm2}14'b10011000000100;
6'd50:{dclkm1,dclkm2}=14'b01001000000001;
6'd51:{dclkm1,dclkm2}=14'b01001001001111;
6'd52:{dclkm1,dclkm2}=14'b01001000010010;
6'd53:{dclkm1,dclkm2}=14'b01001000000110;
6'd54:{dclkm1,dclkm2}=14'b01001001001100;
6'd55:{dclkm1,dclkm2}=14'b01001000100100;
6'd56:{dclkm1,dclkm2}=14'b01001000100000;
6'd57:{dclkm1,dclkm2}=14'b01001000001111;
6'd58:{dclkm1,dclkm2}=14'b01001000000000;
6'd59:{dclkm1,dclkm2}=14'b01001000000100;
endcase

case(clkh)
6'd0:{dclkh1,dclkh2}=14'b00000010000001;
6'd1:{dclkh1,dclkh2}=14'b00000011001111;
6'd2:{dclkh1,dclkh2}=14'b00000010010010;

6'd3:{dclkh1,dclkh2}=14'b00000010000110;
6'd4:{dclkh1,dclkh2}=14'b00000011001100;
6'd5:{dclkh1,dclkh2}=14'b00000010100100;
6'd6:{dclkh1,dclkh2}=14'b00000010100000;
6'd7:{dclkh1,dclkh2}=14'b00000010001111;
6'd8:{dclkh1,dclkh2}=14'b00000010000000;
6'd9:{dclkh1,dclkh2}=14'b00000010000100;
6'd10{dclkh1,dclkh2}=14'b10011110000001;
6'd11:{dclkh1,dclkh2}=14'b10011111001111;
6'd12:{dclkh1,dclkh2}=14'b10011110010010;
6'd13:{dclkh1,dclkh2}=14'b10011110000110;
6'd14:{dclkh1,dclkh2}=14'b10011111001100;
6'd15:{dclkh1,dclkh2}=14'b10011110100100;
6'd16:{dclkh1,dclkh2}=14'b10011110100000;
6'd17:{dclkh1,dclkh2}=14'b10011110001111;
6'd18:{dclkh1,dclkh2}=14'b10011110000000;
6'd19:{dclkh1,dclkh2}=14'b10011110000100;
6'd20:{dclkh1,dclkh2}=14'b00100100000001;
6'd21:{dclkh1,dclkh2}=14'b00100101001111;
6'd22:{dclkh1,dclkh2}=14'b00100100010010;
6'd23:{dclkh1,dclkh2}=14'b00100100000110;
endcase

end

endmodule

5 结论以及结果说明

正常显示时间秒钟模10

该多功能数字钟系统在QuartusⅡ软件上进行调试仿真，后在DE2开发板上进行验证，最终完成设计。设计出的闹钟具有正常时间显示，时间修改，闹钟及秒表功能。
但不足的是还可以加入液晶显示屏。

6 心得体会，及对本课程的建议
通过对本课程的学习，收获很多，主要是对QuartusⅡ的理解和使用，包括对于语言的运用，模块的设计，引脚的使用等 。并且希望实验课程最好设置在数电理论课程同时进行，会理解的更好。