基于Quartus2组件DSP_builder设计DDS信号发生器.docx

基于Quartus2组件DSP_builder设计DDS信号发生器
说明：Quartus2中DSP_builder组件建立了Quartus2与Matlab的无缝链接，这样极大的有利于FPGA在信号处理中的应用，本次课题旨在通过建立一个信号发生器来说明DSP_builder的强大之处。
传统的DDS信号发生器的设计相对比较复杂（包括相位累加器，地址查找表，D/A），通过传统的编程思想，会比较复杂，DSP_builder则是通过simulink中的Altera库，直接构建DDS模型，再通过signal complier生成VHDL语言以及仿真所用的测试脚本（testbench文件），非常方便，并通过simulink和FPGA的仿真工具Modelsim_Atera一起做了对比，两者吻合，达到了预期效果。

1.在Simulink中构建DDS模型

2.Simulink下的仿真如图所示：

3.RTL级仿真（modelsim仿真）：

4.RTL级视图

附：.vhl代码
-- sinwafe_GN.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sinwafe_GN is
port (
Output : out std_logic_vector(7 downto 0); -- Output.wire
Input : in std_logic_vector(0 downto 0) := (others => '0'); -- Input.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic : '0' -- .reset_n
);
end entity sinwafe_GN;

architecture rtl of sinwafe_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;

component alt_dspbuilder_port_GNXAOKDYKC is
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out stdlogic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_port_GNXAOKDYKC;

component alt_dspbuilder_lut_GNV7OH7CRC is
generic (
use_lpm : natural := 0;
reg_addr : natural := 0;
reg_data : natural := 0;
family : string := "STRATIX";

ADDRWIDTH : positive := 8;
DATAWIDTH : positive := 8;
RAMTYPE : string := "AUTO"
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
Input : in std_logic_vector(ADDRWIDTH-1 downto 0) := (others => 'X'); -- wire
Output : out std_logic_vector(DATAWIDTH-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_lut_GNV7OH7CRC;

component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;

component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;

component alt_dspbuilder_product_GNSX3UCWXH is
generic (
pipeline : natural := 0;
UseDedicatedMult : natural := 0;
lpm : natural := 0;
MaskValue : string := "1";
Signed : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width*2-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_product_GNSX3UCWXH;

component alt_dspbuilder_delay_GN53FGQEY3 is
generic (
width : positive := 8;
delay : positive := 1;
ClockPhase : string := "1";
use_init : natural := 0;
BitPattern : string := "00000001"
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GN53FGQEY3;

component alt_dspbuilder_inc_decGNM4UTC62W is
generic (
lpm : natural := 0;
MaskValue : string := "1";
direction : natural := 0;
Unsigned : natural := 0;
StartValue : string := "00000000";
OutputWidth : integer := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputWidth-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_inc_dec_GNM4UTC62W;

component alt_dspbuilder_port_GNA5S4SQDN is
port (
input : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_port_GNA5S4SQDN;

component alt_dspbuilder_cast_GNQDULLOC6 is
generic (
saturate : natural := 0;
round : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNQDULLOC6;

component alt_dspbuilder_cast_GNXB66IQUO is
generic (
saturate : natural := 0;
round : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNXB66IQUO;

component alt_dspbuilder_cast_GNA72OVCRC is
generic (
saturate : natural := 0;
round : natural := 0
);
port (
input : in std_logic_vector(5 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(5 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNA72OVCRC;

signal sin_lutsclrgnd_output_wire : std_logic; -- Sin_LUTsclrGND:output -> Sin_LUT:sclr
signal sin_lutenavcc_output_wire : std_logic; -- Sin_LUTenaVCC:output -> Sin_LUT:ena
signal productuser_aclrgnd_output_wire : std_logic; -- Productuser_aclrGND:output -> Product:user_aclr
signal productenavcc_output_wire : std_logic; -- ProductenaVCC:output -> Product:ena
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal delayenavcc_output_wire : std_logic; -- DelayenaVCC:output -> Delay:ena
signal inccountsclrgnd_output_wire : std_logic; -- IncCountsclrGND:output -> IncCount:sclr
signal inccountenavcc_output_wire : std_logic; -- IncCountenaVCC:output -> IncCount:ena
signal delay_output_wire : std_logic_vector(7 downto 0); -- Delay:output -> Product:dataa
signal sin_lut_output_wire : std_logic_vector(7 downto 0); -- Sin_LUT:Output -> Delay:input
signal input_0_output_wire : std_logic_vector(0 downto 0); -- Input_0:output -> cast0:input
signal cast0_output_wire : std_logic_vector(7 downto 0); -- cast0:output -> Product:datab
signal product_result_wire : std_logic_vector(15 downto 0); -- Product:result -> cast1:input
signal cast1_output_wire : std_logic_vector(7 downto 0); -- cast1:output -> Output_0:input
signal inccount_result_wire : std_logic_vector(5 downto 0); -- IncCount:result -> cast2:input
signal cast2_output_wire : std_logic_vector(5 downto 0); -- cast2:output -> Sin_LUT:Input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Delay:aclr, IncCount:aclr, Product:aclr, Sin_LUT:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Delay:clock, IncCount:clock, Product:clock, Sin_LUT:clock]

begin

clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);

input_0 : component alt_dspbuilder_port_GNXAOKDYKC
port map (
input => Input, -- input.wire

output => input_0_output_wire -- output.wire
);

sin_lut : component alt_dspbuilder_lut_GNV7OH7CRC
generic map (
use_lpm => 1,
reg_addr => 1,
reg_data => 0,
family => "Cyclone II",
ADDRWIDTH => 6,
DATAWIDTH => 8,
RAMTYPE => "AUTO"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
Input => cast2_output_wire, -- Input.wire
Output => sin_lut_output_wire, -- Output.wire
sclr => sin_lutsclrgnd_output_wire, -- sclrwire
ena => sin_lutenavcc_output_wire -- ena.wire
);

sin_lutsclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => sin_lutsclrgnd_output_wire -- output.wire
);

sin_lutenavcc : component alt_dspbuilder_vcc_GN
port map (
output => sin_lutenavcc_output_wire -- output.wire
);

product : component alt_dspbuilder_product_GNSX3UCWXH
generic map (
pipeline => 0,
UseDedicatedMult => 0,
lpm => 0,
MaskValue => "1",
Signed => 1,
width => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => delay_output_wire, -- dataa.wire
datab => cast0_output_wire, -- datab.wire
result => product_result_wire -- result.wire
user_aclr => productuser_aclrgnd_output_wire, -- user_aclr.wire
ena => productenavcc_output_wire -- ena.wire
);

productuser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => productuser_aclrgnd_output_wire -- output.wire
);

productenavcc : component alt_dspbuilder_vcc_GN
port map (
output => productenavcc_output_wire -- output.wire
);

delay : component alt_dspbuilder_delay_GN53FGQEY3
generic map (
width => 8,
delay => 1,
ClockPhase => "1",
use_init => 0
BitPattern => "00000001"
)
port map (
input => sin_lut_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => delayenavcc_output_wire -- ena.wire
);

delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);

delayenavcc : component alt_dspbuilder_vcc_GN
port map (
output => delayenavcc_output_wire -- output.wire
);

inccount : component alt_dspbuilder_inc_dec_GNM4UTC62W
generic map (
lpm => 0,
MaskValue => "1",
direction => 0,
Unsigned => 0,
StartValue => "000000",
OutputWidth => 6
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => inccount_result_wire, -- result.wire
sclr => inccountsclrgnd_output_wire, -- sclr.wire
ena => inccountenavcc_output_wire -- ena.wire
);

inccountsclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => inccountsclrgnd_output_wire -- output.wire
);

inccountenavcc : component alt_dspbuilder_vcc_GN
port map (
output => inccountenavcc_output_wire -- output.wire
);

output_0 : component alt_dspbuilder_port_GNA5S4SQDN
port map (
input => cast1_output_wire, -- input.wire
output => Output -- output.wire
);

cast0 : component alt_dspbuilder_cast_GNQDULLOC6
generic map (
saturate => 0,
round => 0
)
port map (
input => input_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);

cast1 : component alt_dspbuilder_cast_GNXB66IQUO
generic map (
saturate => 0,
round => 0
)
port map (
input => product_result_wire, -- input.wire
output => cast1_output_wire output.wire
);

cast2 : component alt_dspbuilder_cast_GNA72OVCRC
generic map (
saturate => 0,
round => 0
)
port map (
input => inccount_result_wire, -- input.wire
output => cast2_output_wire -- output.wire
);

end architecture rtl; -- of sinwafe_GN