关于MOS布线时的天线效应(Antenna-effect)的解说.docx

关于mos布线的天线效应的解说
The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits.[1][2][3][4][5] Fabs normally supply antenna rules, which are rules that must be obeyed to avoid this problem. A violation of such rules is called an antenna violation. The word antenna is something of a misnomer in this context—the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. Occasionally the phrase antenna effect is used in this context,[6] but this is less common since there are many effects,[7] and the phrase does not make clear which is meant.( e5 P6 t; L5 Y) f0 4 H# C8 X; ^& G1 `4 f/ l:
天线效应，更正式地说叫做 电浆引起的栅氧损伤，在MOS结构的制造过程中可能会带来良率损失或可靠性问题。Fab通常会提供天线效应的设计规范，这条规范设计人员必须遵守。使用Antenna这个单词，从严格意义上说不是太准确，因为这里的天线是用来收集电荷，而不是用于电磁场转换的天线。
Figure 1(a) shows a side view of a typical net in an integrated circuit. Each net will include at least one driver, which must contain a source or drain diffusion (in newer technology implantation is used), and at least one receiver, which will consist of a gate electrode over a thin gate dielectric (see Figure 2 for a detailed view of a MOS transistor). Since the gate dielectric is so thin, only a few molecules thick, a big worry is breakdown of this layer. This can happen if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. (Historically, the gate dielectric has been silicon dioxide, so most of the literature refers to gate oxide damage or gate oxide breakdown. As of 2007, some manufacturers are replacing this oxide with various high-k dielectric materials which may or may not be oxides, but the effect is still the same.)* `7 t7 K5 i' r* i& M8 w' }% O) t
图1是一个典型的IC 互连(天线网)的侧视图，每个天线网至少有一个驱动端(source或drain的扩散区/离子植入区)，至少一个接收端(Gate oxide上的poly silicon电极)。由于Gate介质层很薄，容易发生超过介质层本身耐压能力的击穿。
Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. This protects the gate oxide.
一旦MOS及互连结构形成后，一般就不会发生这种天线效应导致的击穿了，因为每个天线网都至少与一个source或drain的扩散区/离子植入区相连了。source/drain会形成一个二极管，且这个二极管的正向和反向击穿电压，都会比gate-oxide要低。这样就形成了对gate-oxide的保护。
However, during the construction of the chip, the oxide may not be protected by a diode. This is shown in figure 1(b), which is the situation while metal 1 is being etched. Since metal 2 is not built yet, there is no diode connected to the gate oxide. So if a charge is added in any way to the metal 1 shape (as shown by the lightning bolt) it can rise to the level of breaking down the gate oxide. In particular, reactive-ion etching of the first metal layer can result in exactly the situation shown - the metal on each net is disconnected from the initial global metal layer, and the plasma etching is still adding charges to each piece of metal.9 P  r2 J0 K" R( ]8 {. i:
:然而，在互连结构形成的过程中，gate-oxide存在没有被保护的时机。如图1(b)所示，正在蚀刻metal-1的时候，由于metal-2还没有形成，没有保护二极管来对gate-oxide进行放电保护。所以，如果蚀刻电浆(etching ion plasma)中的电荷被加到metal-1上，则有可能会导致gate-oxide发生击穿。3 M* t# b" m" `. E& Q/ K
Leaky gate oxides, although bad for power dissipation, are good for avoiding damage from the antenna effect. A leaky oxide can prevent a charge from building up to the point of causing oxide breakdown. This leads to the somewhat surprising observation that a very thin gate oxide is less likely to be damaged than a thick gate oxide, because as the oxide grows thinner, the leakage goes up exponentially, but the breakdown voltage shrinks only linearly.
由于有轻微漏电的栅氧可以防止电荷累积到击穿临界点，所以虽然它会带来功率损耗，但却可以避免天线效应的不利影响。人们也观察到一个现象，即：相对于厚栅氧，薄一点点的栅氧反而不容易受到天线效应的影响。这里有个实际物理情况，即：随着栅氧厚度变薄，漏电呈指数增长，但耐压却只是线性下降。" D8 b* N" b  ]: n6  Figure 1: Illustration of the cause of antenna effect. M1 and M2 are the first two metal

interconnect layers 
Figure 2. Diagram of a MOSFET, showing source/drain implant and gate dielectric.7 b  {0 ^: Antenna rules 天线规则
Antenna rules are normally expressed as an allowable ratio of metal area to gate area. There is one such ratio for each interconnect layer. The area that is counted may be more than one polygon —it is the total area of all metal connected to gates without being connected to a source/drain implant.+ M$ M. t. q/ M
天线规则，一般以metal和gate的面积比来衡量。每个内互连层都有一个规则比率。计算面积时，只要是与gate连接的metal，且这个metal还没有被连接到某个source/drain，这些metal的面积都要累加起来。9 \; I0 A; ?
If the process supports different gate oxides, such as a thick oxide for higher voltages and a thin oxide for high performance, then each oxide will have different rules.) s  T1 u: }+ P; There are cumulative rules, where the sum (or partial sum) of the ratios over all interconnect layers sets the limit.! z' D4 v$ q; a& R: x6 B) f!
There are rules that consider the periphery of each polygon, as well., R+ n& q% ]+ m& z2
Before signing-off a physical design/layout for fabrication, the Antenna Rule Check is therefore performed.7 K8 O# W- i: O"
Fixes for antenna violations 违反天线规则后的补救方法6 S3 m7 |: H! \( M0 K: e0
In general, antenna violations must be fixed by the router. Possible fixes include:
若发生天线规则不符，则必须通过走线调整来纠正。一般的补救方式有如下几种： # ?2 Change the order of the routing layers. If the gate(s) immediately connects to the highest metal layer, no antenna violation will normally occur. This solution is shown in Figure 3(a).变更层间走线方式。如果gate直接与顶层metal互连，一般不会有天线效应发生(因为与gate直连的metal-1面积很小)。如图3(a)所示。/ W# a5 x4 g( J* P
Add vias near the gate(s) to connect the gate to the highest layer used. This adds more vias, but involves fewer changes to the rest of the net. This is shown in Figure 3(b).
在gate附近增加via。如图3(b)所示。" K+ j+ v0 a$ N* J8 R
Add diode(s) to the net, as shown in Figure 3(c). A diode can be formed away from a MOSFET source/drain for example, with an n+ implant in a p-substrate or with a p+ implant in an n-well. If the diode is connected to metal near the gate(s), it can protect the gate oxide. This can be done only on nets with violations, or on every gate (in general by putting such diodes in every library cell). The "every cell" solution can fix almost all antenna problems with no need for action by any other tools. However, the extra capacitance of the diode makes the circuit slower and more power hungry.7 ~1 s% [/ u$ d& y) `8增加释放电荷的二极管。如图3(c)所示。
二极管可以有MOS的source或drain形成。例如，在p-sub里做n+，或在n-well里做p+。*当然增加二极管，也就带来了额外的电容，使得电路更慢，驱动起来更费力。

Figure 3: Illustration of three possible fixes to an antenna violation.