cadence生成网络表时出现如下错误解决办法.doc

cadence生成网络表时出现如下错误，解决办法（转）
上一篇 / 下一篇  2012-07-16 18:59:32 / 个人分类：PCB设计
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这样吧，一类一类的来分析。
（1）Warning "No_connect"
#1 Warning [ALG0047] "No_connect" property on Pin "P1.8" ignored forP1: SCHEMATIC1, 13)URAT (7.90, 1.20). Connecting pin to net "N16811229".&H)K]hwM
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ALG0047，这个警告基本可以忽略；造成这个问题的原因是，设计之初先对器件相关的管脚上加上'X'(也就是NC符号)，更新设计的过程又对管脚做了连接处理；但是后面的连接处理没有去掉管脚的NC属性，不信的话把那个管脚上的net删掉看看。 RG9f
解决办法很简单，对这些管脚再做一次NC

（2）Warning  Part Name
#5 Warning [ALG0016] Part Name "CAP PN_C100UP-6.3V-SMT-S_100UF/6.3V" is renamed to "CAP PN_C100UP-6.3V-SMT-S_100UF/"
这个警告不可避免，allegro对相关的属性名称进行合并，超过一定数量的字符就截掉；在命名规范的前提下就不考虑这个警告了。
无法根治

这个#2 Warning [ALG0016] Part Name "?j#w?rm
之类的错误在于你建立元件原理图的时候你的原件Value值太长了超过32个字符,从而使系统在进行命名规范的时候溢出,而出错,很简单的,只写关键元件名,比如 A2541P10_HDR2X5-100MIL_2X5 HEADER" is renamed to "A2541P10_HDR2X5-100MIL_2X5 HEAD错误只需要
把2X5 HEADER更改为A2541P10,去除中间的空格即可.

U(ZE0B5L5b%X;n4g Allegro对一些字符[例如"空格","小数点"等等]很在意,可以参阅相关文档的描述.

（3）Error  Illegal character "Dot(.)" found in "PCB Footprint"
#1 Error   [ALG0081] Illegal character "Dot(.)" found in "PCB Footprint" property for component instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08) .
封装命名不能包含“.”

（4）Error  Illegal character "Forward Slash(/)" found in "PCB Footprint" property
#1 Error   [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08) .
#2 Error   [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02) .
#3 Error   [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance C245: PG16_AC97, PG16_AC97 (205.74, 35.56) .
封装命名不能包含“/”

（5）比较隐藏的排除法
Loading... E:\FPGA\SCH\allegro/pstchip.dat
#34 WARNING(SPCODD-34): Expected ';' character on line 5308. Check the name and value syntax for invalid characters in the
primitive definition before the line number.
              ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID The design may not have been saved correctly. Save the schematic and rerun packaging.
#187 Error   [ALG0036] Unable to read logical netlist data.

Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\motherboard.dsn" -n "E:\FPGA\SCH\allegro" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

*** Done*******
掌握排错方法，查找文件pstchip.dat，第on line 5308  看看错误，便可以解决

（6）封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决
********************************************************************************
** Netlisting the design
*********************
Design Name:
E:\FPGA\SCH\basicboard.dsn
Netlist Directory:
E:\FPGA\SCH\allegro
Configuration File:
D:\Cadence\SPB_16.2\tools\capture\allegro.cfg

Spawning... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n "E:\FPGA\SCH\allegro" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Error   [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82) .
#2 Error   [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64) .
#3 Info: PCB Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).

#4 Aborting Netlisting... Please correct the above errors and retry.

Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n "E:\FPGA\SCH\allegro" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

*** Done ***
封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决

（7）Warning
#11 Warning [ALG0051] Pin "GND" is renamed to "GND#A6" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).
#12 Warning [ALG0051] Pin "GND" is renamed to "GND#A11" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).
#13 Warning [ALG0051] Pin "GND" is renamed to "GND#A1" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).
#14 Warning [ALG0051] Pin "GND" is renamed to "GND#W8" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).
这条警告信息，在命名规范的前提下就不考虑这个警告了。
无法根治，除非去除检测

（8）
#60 Warning [ALG0016] Part Name "COM_17×2_SIP17X2_COM_17×2" is renamed to "COM_172_SIP17X2_COM_172".
#61 Warning [ALG0060] No pins are present in J53. Ignoring this component  in netlist.
#62 Warning [ALG0016] Part Name "1X3P,MALE,DIP_2.0_SIP3_1X3P_2.54MM" is renamed to "1X3P,MALE,DIP_2.0_SIP3_1X3P_2.5".
器件管脚不存在，有的器件做了但没放管脚，正常

(9) error: Same Pin Number connected to  more than one net.
请检查 这个器件的位号是否有重复。 一般是重复了才会出现这种情况。

Checking Pins and Pin Connections
ERROR:  [DRC0031]  Same Pin Number connected to  more than one net. LED&Switch&7-Segment Disp/U17/3 Nets: '3V3' and '485_RE/DE'.
                    PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp  (101.85, 73.66)

上面的问题是器件位号重复
（10）
WARNING:  [DRC0008]  Two nets in same schematic have the same name, but there is no off-page connector
这个问题是信号同名，到没有用OFF-PAGE连接起来  生成网表会自动重新命名一个名字