eda练习题1.doc

1、优先级编码器。图是一个7级优先级编码器。如果输入矢量中出现多个'1'，那么电路将优先对最高位编码输出。"000"表示输入矢量中没有出现位'1'，不需要编码输出。使用WHEN/ELSE语句实现该电路。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY encoder IS
PORT ( x: IN bit_VECTOR(7 DOWNTO 1);
y: OUT bit_VECTOR(2 DOWNTO 0));
END encoder;
ARCHITECTURE encoder1 OF encoder IS
BEGIN
y <= "111" WHEN x(7)=’1’ELSE
"110" WHEN x(6)= ’1’ ELSE
"101" WHEN x(5)= ’1’ ELSE
"100" WHEN x(4)= ’1’ ELSE
"011" WHEN x(3)= ’1’ELSE
"010" WHEN x(2)= ’1’ ELSE
"001" WHEN x(1)= ’1’ ELSE
"000" ;
END encoder1;

2、编写实现如图所示状态转移关系的VHDL代码。

library ieee;
use ieee.std_logic_1164.all;
entity fsm is
port( inp,rst,clk:in std_logic;
outp:out std_logic_vector(1 downto 0));
end fsm;
architecture arch of fsm is
type state is(state1,state2,state3,state4);
signal pr_state,nx_state:state;
signal temp:std_logic_vector(1 downto 0);
begin
process(rst,clk)
begin
if(rst='1') then
pr_state<=state1;
elsif(clk'event and clk='1') then
outp<=temp;
pr_state<=nx_state;
end if;
end process;

process(inp,pr_state)
begin
case pr_state is
when state1 =>
temp<="00";
if(inp='1') then
nx_state<=state2;
else
nx_state<=state1;
end if;
when state2 =>
temp<="01";
if(inp='0') then
nx_state<=state3;
else
nx_state<=state4;
end if;
when state3 =>
temp<="10";
if(inp='1') then
nx_state<=state4;
else
nx_state<=state3;
end if;
when state4 =>
temp<="11";
if(inp='1') then
nx_state<=state1;
else
nx_state<=state2;
end if;
end case;
end process;
end arch;
3、通用奇偶校验发生器电路
当输入矢量中'1'的个数分别为奇数和偶数时，所增加的输出位的值相应地为'1'和'0'，这样使得输出矢量中'1'的个数恒为偶数。

1 -------------------------------------------------
2 ENTITY parity_gen IS
3 GENERIC (n: INTEGER := 7);
4 PORT ( input: IN BIT_VECTOR(n-1 DOWNTO 0);
5 output: OUT BIT_VECTOR(n DOWNTO 0));
6 END parity_gen;
7 -------------------------------------------------
8 ARCHITECTURE parity OF parity_gen IS
9 BEGIN
10 PROCESS (input)
11 VARIABLE temp1: BIT;
12 VARIABLE temp2: BIT_VECTOR(output'RANGE);
13 BEGIN
14 temp1 := '0';
15 FOR i IN input'RANGE LOOP
16 temp1 := temp1 XOR input(i);
17 temp2(i) := input(i);
18 END LOOP;
19 temp2(output'HIGH ) := temp1;
20 output <= temp2;
21 END PROCESS;
22 END parity;

4、带7段数码显示的模100计数器，实现一个异步复位的模100累加计数器，此外它还可以将累加的BCD值转换成7段数码显示

。

1 -------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 -------------------------------------------------
5 ENTITY counter IS
6 PORT clk, reset: IN STD_LOGIC;
7 digit1, digit2: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
8 END counter;
9 -------------------------------------------------
10 ARCHITECTURE counter OF counter IS
11 BEGIN
12 PROCESS (clk, reset)
13 VARIABLE temp1: INTEGER RANGE 0 TO 10;
14 VARIABLE temp2: INTEGER RANGE 0 TO 10;
15 BEGIN
16 --counter: -----
17 IF (reset = '1') THEN
18 temp1 := 0;
19 temp2 := 0;
20 ELSIF (clk'EVENT AND clk = '1') THEN
21 temp1 := temp1+1;
22 IF (temp1=10) THEN
23 temp1 := 0;
24 temp2 := temp2+1;
25 IF (temp2=10) THEN
26 temp2 := 0;
27 END IF;
28 END IF;
29 END IF;
30 ---BCD to SSD conversion: ---
31 CASE temp1 IS
32 WHEN 0 => digit1 <= "1111110"; --7E
33 WHEN 1 => digit1 <= "0110000"; --30
34 WHEN 2 => digit1 <= "1101101"; --6D
35 WHEN 3 => digit1 <= "1111001"; --79
36 WHEN 4 => digit1 <= "0110011"; --33
37 WHEN 5 => digit1 <= "1011011"; --5B
38 WHEN 6 => digit1 <= "1011111"; 5F
39 WHEN 7 => digit1 <= "1110000"; --70
40 WHEN 8 => digit1 <= "1111111"; --7F
41 WHEN 9 => digit1 <= "1111011"; --7B
42 WHEN OTHERS => NULL;
43 END CASE;
44 CASE temp2 IS
45 WHEN 0 => digit1 <= "1111110"; --7E
46 WHEN 1 > digit1 <= "0110000"; --30
47 WHEN 2 => digit1 <= "1101101"; --6D
48 WHEN 3 => digit1 <= "1111001"; --79
49 WHEN 4 => digit1 <= "0110011"; --33
50 WHEN 5 => digit1 <= "1011011"; --5B
51 WHEN 6 => digit1 <= "1011111"; --5F
52 WHEN 7 => digit1 <= "1110000"; --70
53 WHEN 8 => digit1 <= "1111111"; --7F
54 WHEN 9 => digit1 <= "1111011"; --7B
55 WHEN OTHERS => NULL;
56 END CASE;
57 END PROCESS;
58 END counter;
5、使用loop语句实现对输入矢量中连续出现的零的个数进行统计
1 ----------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 -------------------------------------------------
5 ENTITY LeadingZeros IS
6 PORT ( data: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
7 zeros: OUT INTEGER RANGE 0 TO 8);
8 END LeadingZeros;
9 -----------------------
10 ARCHITECTURE behavior OF LeadingZeros IS
11 BEGIN
12 PROCESS (data)
13 VARIABLE count: INTEGER RANGE 0 TO 8;
14 BEGIN
15 count := 0;
16 FOR i IN data'RANGE LOOP
17 CASE data(i) IS
18 WHEN '0' => count := count+1;
19 WHEN OTHERS => EXIT;
20 END CASE;
21 END LOOP;
22 zeros <= count;
23 END PROCESS;
24 END behavior;
6、设计一个对时钟进行6分频的电路

1 -------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ------------------------------------------
5 ENTITY freq_divider IS
6 PORT (clk: IN STD_LOGIC;
7 out1, out2: BUFFER STD_LOGIC);
8 EDN freq_divider;
9 -------------------------------------------------
10 ARCHITECTURE example OF freq_divider IS
11 SIGNAL count1: INTEGER RANGE 0 TO 7;
12 BEGIN
13 PROCESS (clk)
14 VARIABLE count2: INTEGER RANGE 0 TO 7;
15 BEGIN
16 IF (clk'EVENT AND clk = '1') THEN
17 count1 <= count1+1;
18 count2 := count2+1;
19 IF (count1 =?) THEN
20 out1 <= NOT out1;
21 count1 <= 0;
22 END IF;
23 IF (coun2=?) THEN
24 out2 <= NOT out2;
25 count2 := 0;
26 END IF
27 END IF;
28 END PROCESS;
29 END example;

Count1=2 count2=3

7、信号发生器

ENTITY sig IS
PORT (clk: IN BIT;
out1,out2: buffer BIT);
END sig;
ARCHITECTURE sig OF sig IS
TYPE state IS (one, two, three,four);
SIGNAL pr_state1, nx_state1: state;
SIGNAL pr_state2, nx_state2: state;
SIGNAL pr_state3, nx_state3: state;
SIGNAL out3, out4,out5: BIT;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
pr_state1 <= nx_state1;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
pr_state2 <= nx_state2;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '0') THEN
pr_state3 <= nx_state3;
END IF;
END PROCESS;
PROCESS (pr_state1)
BEGIN
CASE pr_state1 IS
WHEN one =>
out1 <= '1';
nx_state1 <= two;
WHEN two =>
out1 <= '0';
nx_state1 <= three;
WHEN three =>
out1 <= '0';
nx_state1 <=four;
WHEN four =>
out1 <= '0';
nx_state1 <= one;
END CASE;
END PROCESS;
PROCESS (pr_state2)
BEGIN
CASE pr_state2 IS
WHEN one =>
out3 <= '0';
nx_state2 <= two;
WHEN two =>
out3 <= '1';
nx_state2 <= three;
WHEN three =>
out3 <= '0';
nx_state2 <= four;
WHEN four =>
out3 <= '0';
nx_state2 <= one;
END CASE;
END PROCESS;
PROCESS (pr_state3)
BEGIN
CASE pr_state3 IS
WHEN one =>

out4 <= '0';
nx_state3 <= two;
WHEN two =>
out4 <= '1';
nx_state3 <= three;
WHEN three =>
out4 <= '0';
nx_state3 <= four;
WHEN four =>
out4 <= '0';
nx_state3 <= one;
END CASE;
END PROCESS;
out5<= out3 and out4;
out2<= out1 or out5;
end sig;
8、设计一个自动售货机的控制器电路。该自动售货机销售价格为25美分的糖果。控制器的输入和输出如图所示。输入信号是nickel_in（投入5美分），dime_in（投入10美分）和quarter_in（存放25美分）。另外两个必要的输入是clk（时钟）和rst（复位）。控制器相应地有3个输出：candy_out用于控制发放糖果，nickel_out用于控制找回5美分的零钱，dime_out用于控制找回10美分零钱。

1 -------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 -------------------------------------------------
5 ENTITY vending_machine IS
6 PORT (clk, rst: IN STD_LOGIC;
7 nickel_in, dime_in, quarter_in: IN BOOLEAN;
8 candy_out, nickel_out, dime_out: OUT STD_LOGIC);
9 END vending_machine;
10 -------------------------------------------------
11 ARCHITECTURE fsm OF vending_machine IS
12 TYPE state IS (st0, st5, st10, st15, st20, st25,
13 st30, st35, st40, st45);
14 SIGNAL present_state, next_state: STATE;
15 BEGIN
16 ----Lower section of the FSM (Sec.8.2): ------
17 PROCESS (rst, clk)
18 BEGIN
19 IF (rst = '1') THEN
20 present_state <= st0;
21 ELSIF (clk'EVENT AND clk = '1') THEN
22 present_state <= next_state;
23 END IF;
24 END PROCESS;
25 ----Upper section of the FSM (Sec.8.2): -------
26 PROCESS (present_state, nickel_in, dime_in, quarter_in)
27 BEGIN
28 CASE present_state IS
29 WHEN st0 =>
30 candy_out <= '0';
31 nickel_out <= '0';
32 dime_out <= '0';
33 IF (nickel_in) THEN next_state <= st5;
34 ELSIF (dime_in) THEN next_state <= st10;
35 ELSIF (quarter_in) THEN next_state <= st25;
36 ELSE next_state <= st0;
37 END IF;
38 WHEN st5 =>
39 candy_out <= '0';
40 nickel_out <= '0';
41 dime_out <= '0';
42 IF (nickel_in) THEN next_state <= st10;
43 ELSIF (dime_in) THEN next_state <= st15;
44 ELSIF (quarter_in) THEN next_state <= st30;
45 ELSE next_state <= st5;
46 END IF;
47 WHEN st10 =>
48 candy_out <= '0';
49 nickel_out <= '0';
50 dime_out <= '0';
51 IF (nickel_in) THEN next_state <= st15;
52 ELSIF (dime_in) THEN next_state <= st20;
53 ELSIF (quarter_in) THEN next_state <= st35;
54 ELSE next_state <= st10;
55 END IF;
56 WHEN st15 =>
57 candy_out <= '0';
58 nickel_out <= '0';
59 dime_out <= '0';
60 IF (nickel_in) THEN next_state <= st20;
61 ELSIF (dime_in) THEN next_state <= st25;
62 ELSIF (quarter_in) THEN next_state <= st40;
63 ELSE next_state <= st15;
64 END IF;
65 WHEN st20 =>
66 candy_out <= '0';
67 nickel_out <= '0';
68 dime_out <= '0';
69 IF (nickel_in) THEN next_state <= st25;
70 ELSIF (dime_in) THEN next_state <= st30;
71 ELSIF (quarter_in) THEN next_state <= st45;
72 ELSE next_state <= st20;
73 END IF;
74 WHEN st25 =>
75 candy_out <= '1';
76 nickel_out <= '0';
77 dime_out <= '0';
78 next_state <= st0;
79 WHEN st30 =>
80 candy_out <= '1';
81 nickel_out <= '1';
82 dime_out <= '0';
83 next_state <= st0;
84 WHEN st35 =>
85 candy_out <= '1';
86 nickel_out <= '0';
87 dime_out <= '1';
88 next_state <= st0;
89 WHEN st40 =>
90 candy_out <= '0';
91 nickel_out <= '1';
92 dime_out <= '0';
93 next_state <= st35;
94 WHEN st45 =>
95 candy_out <= '0';
96 nickel_out <= '0';
97 dime_out <= '1';
98 next_state <= st35;
99 END CASE;
100 END PROCESS;
101
102 END fsm;
9、串行数据接收器电路如图所示。它包括串行数据输入端口（din）和并行数据输出端口（data（6:0）），输入端还包括时钟信号。电路还产生了两个指示信号：err（错误指示信号）和data_valid（有效数据指示信号）。输入信号是一个字符流。
每个完整的字符包括10位，第1位是起始位，当它为高时标志着一个字符的开始，电路应开始接收后面的数据。接下来的7位是有效数据，第9位是奇偶校验位，当数据中1的个数是偶数时其值是'0'，否则为'1'。第10位是终止位，如果传输正确，其值应该是'1'。当接收电路发现奇偶校验错误或者结束位不是'1'时将发出错误指示。当数据被正确接收时，存储在内部寄存器中的数据并行出现在data（6:0）上，同时data_valid有效。

1 -------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 -------------------------------------------------
5 ENTITY receiver IS
6 PORT (din, clk, rst: IN BIT;
7 data: OUT BIT_VECTOR(6 DOWNTO 0);
8 err, data_vaild: OUT BIT);
9 END receiver;
10 ----------------------
11 ARCHITECTURE rtl OF receiver IS
12 BEGIN
13 PROCESS (rst, clk)
14 VARIABLE count: INTEGER RANGE 0 TO 10;
15 VARIABLE reg: BIT_VECTOR (10 DOWNTO 0);
16 VARIABLE temp: BIT;
17 BEGIN
18 IF (rst = '1') THEN
19 count : 0;
20 reg := (reg'RANGE => '0');
21 temp := '0';
22 err <= '0';
23 data_vaild <= '0';
24 ELSIF (clk'EVENT AND clk = '1') THEN
25 IF (reg(0) = '0' AND din = '1') THEN
26 reg(0) := '1';
27 ELSIF (reg(0) = '1') THEN
28 count := count+1;
29 IF (count<10) THEN
30 reg(count) := din;
31 ELSIF (count=10) THEN
32 temp := (reg(1)XOR reg(2)XOR reg(3)XOR
33 reg(4)XOR reg(5)XOR reg(6)XOR
34 reg(7)XOR reg(8))OR NOT reg(9);
35 err <= temp;
36 count := 0;
37 reg(0) := din;
38 IF (temp = '0') THEN
39 data_vaild <= '1';
40 data <= reg(7 DOWNTO 1);
41