模拟集成电路的分析与设计：Chapter 15-Phase-Locked Loops.ppt

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,Phase-Locked Loops(PLL,锁相环）,As its name said:The task of a PLL is to lock the phase and frequency of output signal to that of input signal;,Another words:It is a synchronizer of the output signal and input signal.,Simple PLL(1),Phase detector(PD)compares the phases of,V,out,and V,in,generating an error signal;,Low-pass filter(LPF)transfer the error wave to a dc level to the oscillator;,The dc level can control the output frequency by VCO;,In this way,the frequency and phase of,V,out,can be locked to V,in,.,Simple PLL(2),PD,Definition,Exclusive OR gate as phase detector,LPF,Composed of simple components:Resistors and Capacitors,such as following,LPF input,LPF output,Type I PLL(1),Take a look at the linear model of the simple PLL,The open-loop transfer function is given by,A pole at origin,system is called“Type I”,Type I PLL(2),Since LG=,H(s,),the closed-loop gain:,Type I PLL(3),First drawback of Type I PLL:,LPF,ripple of,V,LPF,VCO control accuracy,LPF,n,Trade-off between the settling time()and the ripple on the VCO control,line(V,LPF,)!,Type I PLL(4),Second drawback of Type I PLL:,Acquisition range of Type I PLL is on the order of,LPF,means the loop locks only if the difference between,in,and,out,is less than roughly,LPF,;,LPF,ripple of,V,LPF,but,LPF,acquisition range,Another trade-off for,Type I PLL!,Charge-pump,PLLs,(1),Remedy to solve the drawbacks of Type I PLL:,Addition of frequency detection(FD),.When difference between,in,and,out,is large,FD works to reduce the difference.When the difference is small,PD works to lock the phase of V,in,and,V,out,Charge-pump,PLLs,(2),Can we merge PD and FD to a PFD?,Charge-pump,PLLs,(3),How about use D,flipflop,to construct a PFD?,Initially Q,A,=Q,B,=0,when A change from 0 to 1,Q,A,=1,Q,B,=0;,When B goes high,Q,B,=1,Reset=1,Q,A,=0,Q,B,=0;,The Q,A,pulse shows the time of A leading B,and is called“,UP”pulse,Similarly,Q,B,pulse shows the time of B leading A,called“DOWN”pulse,Charge-pump,PLLs,(4),PFD with charge-pump,When Q,A,pulse(“,UP”pulse,)exists,S,1,closes,I,1,charges C,p,V,out,rises.,Similarly,Q,B,pulse(“DOWN”pulse)exists,S,2,closes,I,2,discharges Cp,V,out,falls,Charge-pump,PLLs,(5),Simple charge-pump PLL,Usually I,1,and I,2,are designed to be equal!,Charge-pump,PLLs,(6),Linear model of simple charge-pump PLL,Contains two imaginary poles,hence called“type II”PLL,Open-loop has 180,o,C phase shift,system unstable,Charge-pump,PLLs,(7),Improvement of simple charge-pump PLL:addition of zero.,Charge-pump,PLLs,(8),Improvement of simple charge-pump PLL:addition of zero.,Charge-pump,PLLs,(9),Improvement of simple charge-pump PLL:addition of C,2,to suppress the initial step of,V,cont,.,To avoid the problem of system unstable,C,2,is about one-fifth to one-tenth of C,P,Charge-pump,PLLs-Nonideal,effects(1),Owing to delays of the transistors,the phase difference smaller than,0,may be fail to open the charge pump to inject the current,.We say the PFD/CP circuit suffers from a,dead zone,equal to,0,around,0,=0,.,Charge-pump,PLLs-Nonideal,effects(2),Dead zone allows the VCO to accumulate random phase error,resulting in,“,jitter(,抖动）,”,effect.,.,Charge-pump,PLLs-Nonideal,effects(3),Slow,jitter y,1,(x)and,fast,jittery,2,(x).,.,Charge-pump,PLLs-Nonideal,effects(4),System response,of slow and fast jitter for input change and VCO change.,.,Input jitter,low pass,because,V,out,cannot track,V,in,when change is too fast;,VCO jitter,high pass,feedback reacts when change is not too fast.,Charge-pump,PLLs-Nonideal,effects(5),Implement of a charge pump,.,.,Problem(1):There exist a delay difference,between,Q,A.,and,Q,B,switches.,Charge-pump,PLLs-Nonideal,effects(6),Remedy:addition of a complementary pass gate,.,.,Charge-pump,PLLs-Nonideal,effects(7),Problem(2):Charge-sharing,.,.,C,Y,C,X,If phase error is zero and I,D1,=|I,D2,|,both S,1,and S,2,on.,.,If C,X,and C,Y,equal but V,cont,is not at the mid-point voltage between V,DD,and ground,there will exist a jump in V,cont,.,J,ump,Charge-pump,PLLs-Nonideal,effects(8),Remedy:Addition of a“bootstrapping”to suppress Charge-sharing,.,.,When S,1,and S,2,off,S,3,and S,4,closed to pin V,X,and V,Y,to V,cont,through a buffer(unity-gain amplifier),.,When S,1,and S,2,turn on,V,X,=V,Y,=V,cont,and there is no jump happened at V,cont,.,Applications of PLLs,-,Frequency Multiplication(,频率倍增）,f,in,=,f,D,=,f,out,/,M,.,=,f,out,=,M f,in,Applications of PLLs,-,Frequency Synthesis,（频率合成）,Use,channel control to control the factor M,and hence to produce different,f,out,Applications of PLLs,-,Skew reduction,（偏移的减小）,(1),There will have a delay when the,clock CK,in,goes through a buffer(i.e.CK,B,).Hence,there exist a skew between CK,B,and D,in,Applications of PLLs,-,Skew reduction,（偏移的减小）,(2),How to remedy the problem?,Use a PLL between CK,in,and CK,B,to reduce the skew!,Applications of PLLs,-,Jitter reduction(1),As said before,PLL can supress the fast change of input signal.If the bandwidth of PLL is designed properly,the input signal jitter faster than PLL bandwidth will be attenuated.,Applications of PLLs,-,Jitter reduction(2),If there is distortion,we can use a D flipflop to shape it and to reduce Jitter;,Sometimes only one channel to transmit the signal,such as optical fiber.In this case,the clock can be trasmitted by D,in,and recovered by a PLL circuit.,Questions for,Chap.15,(1),Plot a diagram of a simple PLL and explain the working principle of it in short.,(2),What drawbacks does the Type I PLL have?Any way to improve it?,(3),What nonideal effects exist in the Charge-pump PLLs?How to solve them?,(4),Describe applications of PLLs.,