D4559_A02_ReliabilityQualificationRequirementsforLead-FreeProducts.doc

PG Engineering Specification Document Number: D4559
Title: Qualification Requirements- Lead Free Product Revision: A02

Dell Controlled Print

Reliability Qualification Requirements for Lead-Free Products

Number: D4559

Revision: A02

Engineers/Owners: Dell Reliability Organization

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Dell Reliability Engineering 23 of 23 10/28/2004101118/24/2004

Table of Contents

1.0 Revision History 3
2.0 Introduction 4
2.1 Purpose/Objective 4
2.2 Scope 4
2.3 Supporting Documents 4
2.4 Procedure 5
3.0 Qualification Requirements for Level 1 6
3.1 Materials Used 6
3.2 Process Information 6
3.3 Component Information 7
3.3.1 Heat Resistance 7
3.3.2 Moisture Sensitivity 7
3.3.3 Lead Plating 8
3.4 Sample Distribution 10
3.5 Assembly and Inspection (this step is not required for Level 2 and Level 3 products where 4.1 applies). 10
4.0 Qualification Requirements for Level 2 11
4.1 Precondition / Assembly 11
4.2 Vibration and Shock 12
4.3 Thermal Cycling 12
4.4 Highly Accelerated Life Testing (HALT) 12
5.0 Qualification Requirements for Level 3 14
5.1 14
5.2 Torsion Testing (for notebook computers only) 14
5.3 BGA Package Coplanarity 15
6.0 Appendix: Pb-Free Risks 16
6.1 Appendix: Examples of Test Flows 17
7.0 References 18
1.0 Revision History 3
2.0 Introduction 4
2.1 Purpose/Objective 4
2.2 Scope 4
2.3 Supporting Documents 4
2.4 Procedure 4
3.0 Qualification Requirements for Level 1 5
3.1 Materials Used 6
3.2 Process Information 6
3.3 Component Information 7
3.3.1 Heat Resistance 7
3.3.2 Moisture Sensitivity 7
3.3.3 Lead Plating 7
3.4 Sample Distribution 9

3.5 Assembly and Inspection (this step is not required for Level 2 and Level 3 products where 4.1 applies). 9
4.0 Qualification Requirements for Level 2 10
4.1 Precondition / Assembly 10
4.2 Vibration and Shock 11
4.3 Thermal Cycling 11
4.4 Highly Accelerated Life Testing (HALT) 11
5.0 Qualification Requirements for Level 3 13
5.1 13
5.2 Torsion Testing (for notebook computers only) 13
5.3 BGA Package Coplanarity 14
6.0 Appendix: Pb-Free Risks 15
6.1 Appendix: Examples of Test Flows 16
7.0 References 17

1.0 Revision History

Revision
ECO
Description
Approved
Date
A00
155640
Initial Release to A00-00
Ed Tinsley
12/17/03
A01
161025
Clarified Reliability scope for process related requirements. Outlined failure modes. Solderability requirements removed. Requirement for component tables removed. Added Sn whisker table. Clarified component delamination criteria per J-STD-020B. Clarified HALT requirement. Reduced the requirements for preconditioning and assembly. Removed ImAg migration testing..
Ed Tinsley
4/28/04
A02
171570
Specified Tin Whisker requirement specific to FFC/FPC. Clarified heat resistance, and MSL requirement, and Tin Whisker requirement. (Mike Ernie)
Ed Tinsley
10/28/04

2.0 Introduction
2.1 Purpose/Objective
This document details Dell Corporation’s requirements for qualification of lead-free printed circuit board assemblies (PCBAs) supplied directly or indirectly to Dell for use in Dell branded products. These requirements are subject to change based on further industry study and technological changes relating to lead-free solders and parts.

This qualification requirements document is to be used in conjunction with Dell P/N D4394 General Specification for Allowable Levels of Lead (Pb) in Dell Products and Dell P/N M4461 which provides Pb-free requirements for individual components used in Dell products.
2.2 Scope
The requirements listed in this document cover lead-free alloys such as SnCu, SnAg or SnAgCu, with liquidus temperatures below 227°C. Exemptions to Pb-free solder are allowed in Dell products according to the latest RoHS RoHS directives (or as determined by Dell’s Environmental group). The Dell preferred Pb-free alloy is SnAgCu in the composition range Sn(3.0-4.0)Ag(0.5-0.9)Cu. Lead-free solder alloys with melting temperature greater than 227°C or those containing Bi, In, or Zn are unacceptable at this time due to reliability, supply, and or corrosion concerns. Preferred component lead finish is matte Sn over 1.3µm Ni, however others are acceptable if Sn whisker risk is mitigated. Preferred board finish is immersion Ag (0.15 - 0.5 µm thick). However other surface finishes will also be acceptable in certain applications (i.e. Ni/Au plated, high temperature rated OSP materials, immersion Sn, etc.).
2.3 Supporting Documents
· Agile accessible via the ValueChain website ( for Suppliers/Vendors.

· General Specification for Allowable Levels of Lead (Pb) in Dell Products (Dell P/N D4394) located in Agile.
· Lead Free Component Requirements (Dell P/N M4461) located in Agile.
· Dell Restricted Material Spec (Dell P/N 6T198) located in Agile.
· Dell Supplier Declaration on Restricted or Banned Materials (Dell P/N 7X435) located in Agile.
· Directive of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment, 2000/159/COD, October 2002. (RoHS Directive)
· Directive of the European Parliament and of the Council on Waste Electrical and Electronic Equipment, 2000/0158/COD, October 2002. (WEEE Directive)
· 91/157/EEC as amended by Directive 98/101/EC, Batteries and accumulators containing certain dangerous substances.
2.4 Procedure
Prior to the start of qualification testing it is expected that the supplier has performed extensive process optimization studies for Pb-free. DOEs should have been run to select the best solder paste material for screen printing and solder joint integrity. Optimum reflow parameters and an acceptable process window should be determined. Necessary wave solder and rework procedures should be finalized and inspection methods determined. It is expected that the process conditions and materials used to build products for qualification are locked-in for the foreseeable future.

This qualification document consists of three levels of testing requirements. The qualification level is based on product complexity, reliability expectations and risk to customers. The Level 1 requirements apply to relatively simple Dell components/products with a lower implied risk of failure due to lead-free materials and processing. Level 2 applies to products with moderate complexity and risk of failure while Level 3 is meant to address more complex Dell products with highest expected reliability. Prior to initiation of testing, the supplier shall obtain written confirmation from Dell of the required qualification level required for their product.

Prior to any testing a detailed test plan should be developed and agreed upon by all involved parties. This plan should include specific tests, testing location, sample sizes, pass/fail criteria, etc. Sample sizes for component level testing and evaluation will be according to specification unless specifically modified by Dell. Reliability evaluation will be performed at a Dell approved test site unless otherwise agreed prior to start of the project.

A control group will be required for comparison purposes and may consist of the same product assembled with SnPb solder or a previous generation of SnPb product of same complexity. Control group type will be determined by mutual agreement between Dell and the supplier.

The qualification criteria listed are in addition to standard qualification testing already expected of the supplier and any used by the supplier to qualify their current processes. Each supplier is required to submit a report detailing the test conditions, sample sizes, evaluation procedures and test results for any testing that was performed separately from Dell requirement.

At Dell discretion, based on coverage of testing already performed and results provided, all or part of the requirements in this document may be modified. In some cases Dell may require additional testing to determine test limits and failure mechanisms associated with certain higher risk components.

3.0 Qualification Requirements for Level 1
This level is reserved for products with lower perceived risk of failure due to introduction of lead-free materials and processing. Products determined to be in this level are relatively simple and constructed exclusively with components such as passives, through-hole and/or coarse pitch (>0.5 mm) surface mount leaded packages. Some exceptions may apply based on specific product application or use environment. To ensure that all materials can survive the elevated temperatures expected with lead free assembly, all components must be evaluated individually prior to assembly. Types of failure mechanisms being screened for include heat damage, moisture induced cracking/delamination, poor solderability, and weak joints.

NOTE: The following information in sections 3.1, 3.2, and 3.3 must be provided to Dell in a timely fashion upon request.
3.1 Materials Used
a) PCB type
b) PCB Manufacturer
c) PCBA Assembler list if sub contracted, In House, sub supplier)
d) PCB glass transition temperature
e) PCB decomposition temperature
f) PCB manufacturer certified heat resistance
g) PCB Thickness
h) PCB # Layers
i) 1 or 2 side populated
j) Pad finish type (i.e.ImAg, OSP, etc.)
k) List the surface mount lead-free alloy (i.e. Sn-3.5Ag-0.9Cu)
l) Solder paste manufacturer and product # (list all suppliers)
m) SIR test results from solder paste supplier.
n) Flux type (no clean, water soluble, etc.)
o) Wave solder Pb-free alloy
p) Hand Solder / Rework (Wire) Pb free alloy
3.2 Process Information
The information requested below is important to both supplier quality and reliability engineering in relation to lead free process and reliability impact. The questions are meant to establish a baseline for these items relative to initial lead free process management and will be evaluated by both SQE and Reliability. Ongoing processes and controls will be managed by the Supplier Quality organization.

1. Is the product built with a single or dual reflow process?
2. List the peak temperature distribution across the PCBA/Panel.
3. Time within +/-5C of peak.
4. List the time above liquidus temperature.
5. Provide time / temperature reflow profile. Provide location on PCB / Panel for thermocouple probes (attach picture / diagram) and temperatures for those locations during the reflow process.
6. List the minimum peak solder joint temp measured on board (under highest thermal mass component).
7. Wave solder process flow and maximum solder pot temperature / duration (if applicable).
8. Soldering iron temperature (Temp +/-) for rework and hand solder. Maximum allowable hand-solder duration.
9. Provide general overview of part storage and factory floor management for components according to MSL level (for moisture sensitive components). Detailed part management is subject to on site audit.
10. Is nitrogen used in reflow?
11. Procedures for rework to include inspection criteria and soldering iron temperature.
12. Inspection criteria used for lead-free solder joints. This will include criteria for sub contracted assemblies.
13. Provide general overview regarding isolation and tracking of leaded components / materials from Pb-free components / materials. Detailed part management is subject to on site audit.
3.3 Component Information
3.3.1 Heat Resistance
All components used to build a Pb-free product must be rated for temperatures at least 10°C higher than peak assembly process temperature. Heat resistance testing should be performed following MIL-STD 202G #210F with 90-120sec above Pb-free solder liquidus with ≥ 10 seconds at or above peak (10C). or equivalent. Deviation for time above liquidus may be allowed based on process TAL (must be a minimum of 20% greater than process TAL). MIL-STD-202G #210F should be followed for wave solder and soldering iron heat resistance. Deviation may be allowed for TAL based on actual process. MIL-STD-202G #210F should be followed for wave solder and soldering iron heat resistance evaluation. Components that are hand soldered, reworked, or touched up should be rated for a soldering iron temperature of at least 10°C higher than process conditions. Recommended minimum sample size is 10/lot for 3 lots.
3.3.2 Moisture Sensitivity
Determining the moisture level for surface mount components should be done following J-STD-020C for Pb-free or JEITA ED 4701 (Test Method 301A for Pb-Free). Components qualified to J-STD-020B may be acceptable if temperature rating is deemed sufficient. Sample sizes are defined in the specifications as well as inspection and pass/fail criteria. A minimum of 3 reflows is required. A minimum of 60 seconds above liquidus or duration 20% higher than actual reflow process time above liquidus (whichever is longer) is required. SMT type components that are wave soldered will follow procedures detailed in JEITA ED 4701 (Test Method 301A for Pb-Free). A minimum of Level 3 (JEDEC) or Level E (JEITA) is required for all components. Level 4 components (JEDEC) or Level F/G (JEITA) may be approved if factory management is considered acceptable by Dell. Components that do meet minimum of Level 4 or above are not acceptable.

3.3.3 Lead Plating
The Pb-free lead plating material is important in evaluating the risk for tin whiskers. Table 1 outlines requirements for Tin Whisker testing for plating materials determined to be a risk. Finer pitch components plated with Sn based lead finish are most susceptible to shorting due to whisker growth. A 1.31.3 μm nickel underplate is preferred for Sn finishes as this prevents copper diffusion into the Sn which contributes to compressive stress in the Sn layer (the primary driving force for Sn whiskers for Cu base material). SnCu plating is known to be a high risk for Sn whisker growth and should be avoided when possible (bright Sn is the highest risk and not acceptable for use in Dell products without consent). Lead plating situations as outlined in tabl