数字集成电路设计与分析.doc

问答：Point out design objects in the figure such as :design, cell, reference, port, pin, net, then write a command to set 5 to net ADesign: topReference: ADD DFFCell: U1 U2Port: A B clk sumPin: A B D QNet: A B SINSet_load 5 get_nets Awhy do we not choose to operate all our digital circuits at these low supply voltages? 答：1）不加区分地降低电源电压虽然对减少能耗能正面影响，但它绝对会使门的延时加大 2）一旦电源电压和本征电压（阈值电压）变得可比拟，DC特性对器件参数（如晶体管阈值）的变化就变得越来越敏感3）降低电源电压意味着减少信号摆幅。虽然这通常可以帮助减少系统的内部噪声（如串扰引起的噪声），但它也使设计对并不减少的外部噪声源更加敏感）问道题：1. CMOS静态电路中，上拉网络为什么用PMOS,下拉网络为什么用NMOS管2. 什么是亚阈值电流，当减少VT时，VGS =0时的亚阈值电流是增加还是减少？3. 什么是速度饱和效应4. CMOS电压越低，功耗就越少？是不是数字电路电源电压越低越好，为什么？5. 如何减少门的传输延迟？ P2036. CMOS电路中有哪些类型的功耗？7. 什么是衬垫偏置效应。8. gate-to-channel capacitance CGC,包括哪些部分VirSim有哪几类窗口3-6. Given the data in Table 0.1 for a short channel NMOS transistor withVDSAT = 0.6 V and k=100 A/V2, calculate VT0, , , 2|f|, and W / L:解答: 对于短沟道器件： 在选择公式的时候，首先要确定工作区域，表格中的所有VDS均大于VDSAT，所以不可能工作在线性区域。如果工作在饱和区域则： VT 应该满足 : VGS-VTVDSAT 2-VT0.6 1.4VT这是不可能的，所以可以假设所有的数据都是工作在速度饱和区域 所以： 由 1&2 () 所以 1,2,3是在速度饱和区由 2&3 由 2&4 1297/1146=（2-Vt0）x0.6-o.62/2/(2-Vt)x0.6-0.62/2Vt=0.587V由 2 &5 Vt=0.691V这两个值都满足 Vt tpHL 因为 RL=75kW 远大于有效线性电阻 effective linearized on-resistance of M1.5-5 The next figure shows two implementations of MOS inverters. The first inverter uses onlyNMOS transistors. Calculate VOH, VOL, VM for each case. 有的参数参考表1解答：电路 A.VOH: 当 M1关掉， M2 的阈值是:当下面条件满足的时候，M2将关闭: 所以 VOUT=VOH=1.765VVOL: 假设VIN=VDD=2.5V.我们期望 VOUT 为低, 因此我们可以假设M2工作在速度饱和区，而M1工作在线性区域.因为 ID1= ID2 , 所以 VOUT=VOL=0.263V, 假设成立VM: 当VM=VIN=VOUT.假设两晶体管均工作在速度饱和区域, 我们得到下面两个方程: 设 ID1=ID2, 得到 VM=1.269V电路 B.当 VIN=0V, NMOS 关掉，PMOS 打开，并把VOUT拉到VDD, so VOH=2.5. 同样, 当 VIN=2.5V, the PMOS关掉，NMOS 把 VOUT拉到地, 所以VOL=0V.为了计算 VM ： VM=VIN=VOUT.假设两晶体管均工作在速度饱和区域，可以得到下面两组方程.设 ID3+ ID2 =0 ,可以得到r VM = 1.095V.所以假设两晶体管均工作在速度饱和区域是正确的.5-7 Consider the circuit in Figure 5.5. Device M1 is a standard NMOS device. Device M2 has allthe same properties as M1, except that its device threshold voltage is negative and has a valueof -0.4V. Assume that all the current equations and inequality equations (to determine themode of operation) for the depletion device M2 are the same as a regular NMOS. Assume thatthe input IN has a 0V to 2.5V swing. ( VDSAT=0.63v)a. Device M2 has its gate terminal connected to its source terminal. If VIN = 0V, what is theoutput voltage? In steady state, what is the mode of operation of device M2 for this input?b. Compute the output voltage for VIN = 2.5V. You may assume that VOUT is small to simplifyyour calculation. In steady state, what is the mode of operation of device M2 for thisinput?解答 a当 VIN = 0V ， M1则关掉. M2开， 因为 VGS=0 VTn2.所以没有电流通过 M2, M2的源漏电压等于0，故M2工作在线性区域，所以VOUT=2.5V.Solution b假设 M1工作在线性区域， M2工作在速度饱和区域，这就意味：因为Vout很小，所以可以忽略V2out/2,所以可以得到因此我们的假设是合理的。5-15 Sizing a chain of inverters.a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with inputcapacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in Figure， Assume that the propagation delay of a minimum size inverter is 70 ps. Also assumethat the input capacitance of a gate is proportional to its size. Determine the sizing of thetwo additional buffer stages that will minimize the propagation delay.b. If you could add any number of stages to achieve the minimum delay, how many stageswould you insert?What is the propagation delay in this case? 解答a : 当每个buffer的延迟相等的时候，可以得到最小延迟时间.此时每个buffer的尺寸系数分别为 f, f2 解答 b: 最小延迟时间发生在 f = e的时候，因此 6-1 Implement the equation using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance?解答：因为最坏的上拉电阻发生在，只有一个通路存在output node to Vdd.如： ABCDEFG=1111100 and 0101110.最好的上拉电阻发生在： ABCDEFG=0000000.最坏的下拉电阻发生在，只有一个通路存在output node to GND.如： ABCDEFG=0000001 and 0011110.最好的下拉电阻发生在： ABCDEFG=1111111.5章Assume an inverter in the generic 0.25 m CMOS technology designed with a PMOS/NMOS ratio of 3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W/L =1.5). Please compute VIL, VIH, NML, NMH the process parameters is presented in table1解：我们首先计算在VM (= 1.25 V)的增益 所以： VIL=1.2V, VIH=1.3V, NML= NMH=1.21.How to deduce that the propagation delay of a gate ? p203o Keep capacitances(CL) smallo Increase transistor sizes(W/L)o Increase VDD (see figure 5.22)减小CL: 增加晶体管的W/L，提高VDD2.Determine the sizes of the inverters in the circuit of Figure 5.22, such that the delay between nodes Out and In is minimized. You may assume that CL = 64 Cg,1 P210Figure 5.22,3. For the circuit of Figure 4.11, assume that a driver with a source resistance of is used to drive a 10 cm long, 1 mm wide Al1 wire. And assume that the total lumped capacitance for this wire equals 11 pF. When applying a step input(with Vin going from 0 to v), please compute the propagation delay of the circuit. P151 Figure 4.11 解答：4 please analyze intrinsic capacitances of MOSFET transistor ,write out three sources of it, and draw out MOSFET transistor capacitance model. P112答：基本的MOS结构，沟道电荷以及漏和源反向偏置pn结的耗尽区。电容器件模型如下：5 .please write out the expression of equivalent resistance Req of the circuit in Figure 1 when (dis)charging a capacitor. Assuming that the supply voltage VDD is substantially greater than the velocity-saturation voltage VDSAT of the transistor. the channel-length modulation factor ()cannot be ignored in this analysis, are known parameters . P105解答：Program1. please write out verilog code and test bench for a 4 bit up-counter Module counter (clk, reset, enable,count);Input clk, reset, enable;Output3:0 count;Reg3:0 count;Always (posedge clk)If (reset=1b1) Count =0; Else if (enable=1b1) Count =count +1;EndmoduleModule counter_tb; Reg clk, reset, enable; Wire3:0 count; Counter U0(clk, reset, enable, count); Initial BeginClk=0;Reset=0;Enable=0; End Always#5 clk=!clk;initial begin $monitor($time, , , “clk=%d reset=%d enable=%d count=%d”, clk,reset,enable,count); #100 $finish end endmodule 2. please write out verilog code and test bench for a bit full adderModule addbit (a, b, ci ,sum, co );Input a,b,ci;Output sum.co;Wire a,b,ci,sum,co;Assign co,sum=a+b+ci;Endmodulemodule test_for_addbit;reg a, b, ci ;addbit u1(a, b, ci ,sum, co);initialbegin a = 0; b = 0; ci=0;#10a = 0; b = 0; ci=1;#10a = 0; b = 1; ci=0;#10a = 0; b = 1; ci=1;#10a = 1; b = 0; ci=0;#10a = 1; b = 0; ci=1; #10 a = 1; b = 1; ci=0; #10 a = 1; b = 1; ci=1;#10$finish;endinitial$monitor( $time, “ a=%b b=%b ci=%b sum=%b co=%b”, a,b,ci,sum, co );endmodule3.please write out verilog code and test bench for 4-1 MUXmodule mux (a,b,c,d,sel,y);input a,b,c,d;input1:0sel;output y;reg y;always (a or b or c or d or sel)case (sel)o: y=a;1:y=b;2: y=c;3: y=d;Default:$display(“error in sel);EndcaseEndmodulemodule test_for_mux;reg a,b,c,d,sel;/ 调用DUTmux u1(a,b,c,d,sel,y);/ 产生测试激励信号initialbegin a = 0; b = 1; c=0;d=0;sel = 01;#10a = 1;b=0;sel=00;#10c = 1;a=0; sel=10;#10c=0;d=1;sel=11;#10a = 1;b=0;sel=01;#10c = 1;a=0; sel=11;#10$finish;end/ 检测输出信号initial$monitor( $time, “ a=%b b=%b c=%b sel=%b y=%b”, a,b,c,d,sel,y );endmodule4 please write out verilog code and test bench for a 4 bit half adder Module adder (a,b,sum,carry) Input3:0 a,b; Output3:0sum; Output carry; Reg3:0 sum; Reg carry; Always ( a or b) Begin carry, sum=a+b; End Endmodulemodule test_for_adder;reg3:0 a, b;/ 调用DUTadder u1(a,b,sum,carry);/ 产生测试激励信号initialbegin a = 4b0000; b = 4b0001; #10a = 4b0001; b = 4b1001;#10a = 4b0010; b = 4b0101; #10a = 4b0100; b = 4b1001; #10a = 4b1000; b = 4b1101; #10a = 4b1001; b = 4b1111; #10 a = 4b1100; b = 4b1010; #10 a = 4b1101; b = 4b0011;#10$finish;end/ 检测输出信号initial$monitor( $time, “ a=%b b=%b sum=%b carry=%b”, a,b, sum, carry);Endmodule