svpwm源程序.doc

/ TI File $Revision: /main/8 $
// Checkin $Date: April 21, 15:41:53 $
//###########################################################################
//
// FILE: Example_2833xEPwmUpDownAQ.c
//
// TITLE: 空间电压矢量产生程序SVPWM
//
// ASSUMPTIONS:
//
// This program requires the DSP2833x header files.
//
// Monitor ePWM1-ePWM3 pins on an oscilloscope as described
// below.
//
// EPWM1A is on GPIO0-------5脚
// EPWM1B is on GPIO1-------6脚
//
// EPWM2A is on GPIO2-------7脚
// EPWM2B is on GPIO3-------10脚
//
// EPWM3A is on GPIO4-------11脚

// EPWM3B is on GPIO5-------12脚
//

//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, $
//###########################################################################

include "DSP28x_Project.h" // Device Headerfile and Examples Include File
// Prototype statements for functions found within this file.
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void svpwmGen(void);
interrupt void svpwm_isr(void);
volatile float Ualpha,Ubeta;
volatile float A,B,C;
volatile float T0,T1,T2,T3,T4,T5,T6;
volatile float Taon,Tbon,Tcon;
float Ua,Ub,Uc;
float Ts;
int a,b,c;
int N= 0,sector= 0;
#define TPRD 800
#define Udc 800

void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();

// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example

// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the DSP2833x_EPwm.c file
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1INT = &svpwm_isr;
//PieVectTable.EPWM2_INT = &epwm2_isr;
//PieVectTable.EPWM3_INT = &epwm3_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example

// For this example, only initialize the ePWM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

// Step 5. User specific code, enable interrupts:

// Enable CPU INT3 which is connected to EPWM1-3 INT:
IER |= M_INT3;

// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
//PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
//PieCtrlRegs.PIEIER3.bit.INTx3 = 1;

// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;)
{
asm(" NOP");
}

}//main结束

//=======================================================================

interrupt void svpwm_isr(void)
{

svpwmGen();

// Set Compare values
EPwm1Regs.CMPA.half.CMPA = Taon; // adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = Tbon; // adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = Tcon; // adjust duty for output EPWM3A

// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;

// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

}

void InitEPwm1Example()
{
// Setup TBCLK
EPwm1Regs.TBPRD = TPRD; // TPRD=800,Period = 1600 TBCLK counts
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; //////////////////////////Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; ///////////////////// Sync down-stream module
// Setup Tpwm
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT

EPwm1Regs.TBCTL.bit.CLKDIV = 5; //原为TB_DIV1， 对于上下计数：Tpwm = 2 x TBPRD x TTBCLK Fpwm = 1 / (Tpwm)
//Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTLbit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
// Set Dead-band
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC // Active Hi complementary
EPwm1Regs.DBFED = 50; // FED = 50 TBCLKs
EPwm1Regs.DBRED = 50; // RED = 50 TBCLKs

// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
/*
// Set Compare values
//==============================================================
EPwm1Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A
*/

}

void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBPRD = TPRD; // TPRD=800,Period = 1600 TBCLK counts
EPwm2Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; ////////////////////////////// Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; /////////////////////////// sync flow-through
// Setup Tpwm
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 5; // For Up and Down Count--Tpwm = 2 x TBPRD x TTBCLK; Fpwm = 1 / (Tpwm)
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
// Set Dead-band
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBFED = 50; // FED = 50 TBCLKs
EPwm2Regs.DBRED = 50; // RED = 50 TBCLKs
// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event

// Set Compare values

}

void InitEPwm3Example()
{
// Setup TBCLK
EPwm3Regs.TBPRD = TPRD; // TPRD=800,Period = 1600 TBCLK counts
EPwm3Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; //////////////////////////////// Slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; ////////////////////////////// sync flow-through
// Setup Tpwm
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = 5; // For Up and Down Count:Tpwm = 2 x TBPRD x TTBCLK; Fpwm = 1 / (Tpwm)
// Setup shadowing
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM3A
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
// Set Dead-band
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm3Regs.DBFED = 50; // FED = 50 TBCLKs
EPwm3Regs.DBRED = 50; // RED = 50 TBCLKs
// Interrupt where we will change the Compare Values
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event

// Set Compare values

}

void svpwmGen(void)
{

//clarke
Ualpha= 0.6666667*(Ua-0.5*Ub-0.5*Uc);// 0.8660254 = sqrt(3)/2
Ubeta = 0.6666667*(0.8660254*Ub-0.8660254*Uc );//0.6666667=2/3

//sector
A= Ubeta;
B= 1.7320508*Ualpha-Ubeta;
C= -1.7320508*Ualpha-Ubeta;
if(A>= 0) {a= 1;} else a= 0;
if(B>= 0) {b= 1;} else b= 0;
if(C>= 0) {c= 1;} else c= 0;
N=a+2*b+4*c;
switch(N)
{
case 1: sector = 2; break;
case 2: sector = 6; break;
case 3: sector = 1; break;
case 4: sector = 4; break;
case 5: sector = 3; break;
case 6: sector = 5; break;
default: break;
}

//Time
Ts=2*TPRD;///////////////////Ts为开关周期与载波周期（计数周期）相等
if(sector== 1)
{
T1= 1.5*Ts*(Ualpha-0.5773503*Ubeta)/Udc;//0.5773503=1/sqrt(3)
T2= 1.7320508*Ts*Ubeta/Udc;
T0= Ts-T1-T2;

if(T1+T2>Ts)
{
T1= T1*Ts/(T1+T2);
T2= T2*Ts/(T1+T2);
T0= Ts-T1-T2;
}

}

else if(sector== 2)
{
T2= 1.5*Ts*(Ualpha+0.5773503*Ubeta)/Udc;
T3= 1.5*Ts*(0.5773503*Ubeta-Ualpha)/Udc;
T0= Ts-T2-T3;
if(T2+T3>Ts)
{
T2= T2*Ts/(T2+T3);
T3= T3*Ts/(T2+T3);
T0= Ts-T2-T3;
}

}

else if(sector== 3)
{
T3= 1.7320508*Ts*Ubeta/Udc;
T4= 1.5*Ts*(Ualpha+0.5773503*Ubeta)/Udc;
T0= Ts-T3-T4;
if(T3+T4>Ts)
{
T3= T3*Ts/(T3+T4);
T4= T4*Ts/(T3+T4);
T0= Ts-T3-T4;
}

}

else if(sector== 4)
{
T4= 1.5*Ts*(0.5773503*Ubeta-Ualpha)/Udc;//0.5773503=1/sqrt(3)
T5= 1.7320508*Ts*Ubeta/Udc;
T0= Ts-T4-T5;
if(T4+T5>Ts)
{
T4= T4*Ts/(T4+T5);
T5= T5*Ts/(T4+T5);
T0= Ts-T4-T5;
}

}

else if(sector== 5)
{
T5= -1.5*Ts*(Ualpha+0.5773503*Ubeta)/Udc;
T6= -1.5*Ts*(0.5773503*Ubeta-Ualpha)/Udc;
T0= Ts-T5-T6;
if(T5+T6>Ts)
{
T5= T5*Ts/(T5+T6);
T6= T6*Ts/(T5+T6);
T0= Ts-T5-T6;
}

}

else if(sector== 6)
{
T6= -1.7320508*Ts*Ubeta/Udc;
T1= 1.5*Ts*(Ualpha+0.5773503*Ubeta)/Udc;
T0= Ts-T6-T1;
if(T6+T1>Ts)
{
T6= T6*Ts/(T6+T1);
T1= T1*Ts/(T6+T1);
T0= Ts-T6-T1;
}

}

//Switch Time
switch(sector)

{
case 1:
{
Taon= T0/4+T1/2+T2/2;
Tbon= T0/4+T2/2;
Tcon= T0/4;
}break;
case 2:
{
Taon= T0/4+T3/2;
Tbon= T0/4+T2/2+T3/2;
Tcon= T0/4;
}break;
case 3:
{
Taon= T0/4;
Tbon= T0/4+T3/2+T4/2;
Tcon= T0/4+T4/2;
}break;
case 4:
{
Taon= T0/4;
Tbon= T0/4+T5/2;
Tcon= T0/4+T4/2+T5/2;
}break;
case 5:
{
Taon= T0/4+T6/2;
Tbon= T0/4;
Tcon= T0/4+T5/2+T6/2;
}break;
case 6:
{
Taon= T0/4+T6/2+T1/2;
Tbon= T0/4;
Tcon= T0/4+T1/2;
}break;
default: break;
}

}//svpwmGen(void)结束