东南大学信息学院-poc实验报告.docx

东南大学信息学院-poc实验报告Computer Organization and Architecture COURSE DESIGNA Parallel Output Controller- (POC)Southeast universitySchool of Information Science and Engineering1. Design purposea. The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The ISE 14.7 EDA tool is recommended and provided for simulation.b. Learn about the using of Bi-directional Data Bus (BDB), and use a parallel Bi-directional Data Bus to finish the data transmission between CPU and POC.2. Introduction and TasksPOC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheralFigure 1. System structure diagramAs Fig.1 shows the inner connecting of a printer to the system bus through the POC. The com- munication between POC and the printer is controlled by a “handshake” protocol given in Fig.2.Figure 2. The handshake-timing diagram between POC and the printerThe handshaking process is described as follows: When the printer is ready to receive a char- acter, it holds RDY=1. The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the characterat PD and hold RDY at 0 until the character has been printed (e.g. delay 5 or 10ms), then set RDY to 1 again when it is ready to receive the next character.The buffer register BR is used to temporarily hold a character sent from the processor, which char- acter will be transferred to the printer later.The status register SR is used for two control functions:SR7 serves as a ready flag to indicate POC is ready or not to receive a new character from the processor.SR0 is used to enable the interrupt requests sent by POC.In interrupt mode, If SR0=1, then POC will send an interrupt request signal to processor when it is ready to receive a character (i.e., when SR7=1).If SR0=0, then POC will not interrupt.The transfer of a character to POC via the system bus proceeds as follows:In interrupt mode, SR0 is always 1.After sending character to printer, POC sets the SR7 to 1, since SR0=1, the interrupt request signal (IRQ) is set to 0, which indicate an effective interrupt signal to the processor.1、processor sets the value of SR7 &sets the value of BRWhen the processor detects the effective IRQ signal, the processor directly selects BR and writes a character into BR, (processor will never read the state of SR7, which is different with polling mode.)Then the processor sets the SR7 to 0, which indicates that the new character has been written intoBR and not printed yet.2、POC reads and sets the value of SR7& handshakes operations with the printerWhen POC detects that SR7 is set to 0, POC then proceeds to start the handshaking operations with the printer.After sending character to printer, POC sets the SR7 to 1, which indicates POC is ready to receive another character from the processor. The transfer cycle can now repeat.（ and are same with the polling state）PS: During the handshaking operations between POC and printer, the processor does not try to access POC until it receives the interrupt request signal3. The overall connection of the simulated printer and POC expressed in the top module formFigure 3. The top module form of the project4. Design description of the simulation input waveformsThe input and output of CPU,POC and printer are shown below:ProcessorjPinsDescriptionInputclkInput the clock for the CPU running.modeChoose the mode for printing.When mode=1,select a interrupt mode.IRQReceive the interrupt signal IRQ.When IRQ=1 , new data can be sent.DIN7.0Read data from poc.DOUT7.0Write data into poc.OutputrwShow the direction of the DOUT7.0 and DIN7.0 When rw=0, read data from POC.When rw=1, write data to POC.A0Control the address read and write on POC.When A0=0, choose SR.When A0=1, choose BR.CSCS=1, poc work.data7.0The data send to POC to be printedPOCPinsDescriptionInputclkInput the clock for the POC running.RWShow the direction of the DOUT7.0 and DIN7.0 When rw=0, send data to CPU.When rw=1, read data from CPU.A0Input address,When A0=0, choose BR. When A0=1, choose SR.RDYInput the ready signal from printer. When RDY=1, the printer is idle.When RDY=0, the printer is busy.CSInput the mode of the POC.When CS=0,select a polling mode. When CS=1,select a interrupt mode.data7.0The data receive from CPU to be printed.OutputPD7.0Output the data to printer.IRQOutput the interrupt signal IRQ to CPU,showing the POC and printer is ready.TRThe response to print RDY signal, a one-cycle pulse at the port TR(transfer request) shows that new data is sent to printer.DOUT7.0CS=0POC send the state of SR to CPU ;CS=1CPU read the data write in BRSignalSR7.0The register contains the flags for the POC. When SR(7)=1, its idle.When SR(7)=0, its busy.BR7.0The register holds the value of data to print.printerPinsDescriptionInputclkInput the clock for the printer running.TRInput the pulse signal from POC, to show new data is coming.PD7.0Input the data from POC.OutputRDYOutput RDY signal,when RDY=1, it shows printer is waiting for new data.5. Simulation resultsConnection between cpu and pocConnection between poc and printerHere are the explanations of the simulation wave:interrupt mode:1、In the interrupt mode,mode is always set 1, the print process occures by the IRQ signal from poc.2、When S(7)=0, IRA send 0 to cpu, it means there is a print requirement and cpu begin to handle it. 3、 In the interrupt process RW and A0 are singals from cpu to poc to control the action of poc.RW=1 and A0=1 write data from cpu(D) to poc(BR), means the begin of the interrupt process.RW=x and A0=x means there is no interrupt requirement .4、After sending datas to BR and set sr to “00000000”, if RDY=1, poc give a impulse in TR to make the printer begin to work. After the TR signal we can see that the input RDY signal from the printer change from 1 to 0, which shows that the TR signal really make the printer work. 5、After data of BR has been transmitted into printer, poc set SR to “10000001” itself to indicate that it comes to ready and can get the next print task.6、Let data plus 1 to indicate the next new print cycle.6. Conclusion and Discussions1、As a parallel output controller ,poc module to act as an interface between cpu and printer. Form the simulation wave, we can see that my program meets the designs requirements.2、I divide the system into three parts, and one top entity. And I use two way to finishthe top entity. One is write program with vhdl language and another is create aschematic type file and connect wire.3、By designing the POC module, I find it helps to learn how to use of quartus and VHDL for design and simulation.The process of designing also teachs me the importantce of figuring out the struc- ture and timing of the task before programming .Appendix:The program of processor:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity processor isport(clk : in std_logic;IRQ : in std_logic;DOUT : out std_logic_vector(7 downto 0):=00000000;RW : out std_logic:=0;-0read,1writeA0 : out std_logic:=0;-0sr,1brDIN : in std_logic_vector(7 downto 0);end processor;architecture Behavioral of processor issignal data:std_logic_vector(7 downto 0):=00000000;signal mode:std_logic:=1;-默认为中断模式beginprocess(clk)begin if clkevent and clk=1 thenif mode=1 then if IRQ=0 then A0=1; RW=1;-写入数据到BR data=data+00000001;-代表传输的字符 DOUT=data; else A0=X; RW=X;-读入SR的数据 end if; end if;end if;end process;end Behavioral;the program of poc:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.ALL;use ieee.std_logic_unsigned.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity poc isport(A0 : in std_logic;RW : in std_logic;clk : in std_logic;CS : in std_logic:=1;RDY : in std_logic;IRQ : out std_logic:=1;DOUT : out std_logic_vector(7 downto 0);PD : out std_logic_vector(7 downto 0);TR : out std_logic:=0;DIN : in std_logic_vector(7 downto 0);end poc;architecture Behavioral of poc issignal SR : std_logic_vector(7 downto 0):=10000001;signal BR : std_logic_vector(7 downto 0):=00000000;signal count:integer range 0 to 5:=0;type state_type is (s0,s1,s2);signal state: state_type:=s0;beginprocess(clk)begin if clkevent and clk=1 then TR=0; IRQ-中断请求信号 if SR(7)=1 then IRQ=0;-中断请求state=s1; else IRQ=1;state-读入读出选择 if RW=1 and A0=1 then-cpu写入数据到BR BR=DIN; SR(7)=0;state=s2; elsif RW=0 and A0=0 then-cpu读入SR的数据 DOUT=SR; elsif RW=1 and A0=0 then-cpu写入数据到SR SR=DIN; elsif RW=0 and A0=1 then-cpu读入BR的数据 DOUT-打印机 if RDY=1 then TR=1; PD=BR; SR(7)=1; end if;state=s0; end case;end if;end process;end Behavioral;the program of printer:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.ALL;use ieee.std_logic_unsigned.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity print isport(RDY : out std_logic:=1;TR : in std_logic;PD : in std_logic_vector(7 downto 0);clk : in std_logic);end print;architecture Behavioral of print issignal count: integer range 0 to 5:=0;signal data: std_logic_vector(7 downto 0);signal ready:std_logic;beginprocess(clk,TR)begin if clkevent and clk=1 then if TR=1 then RDY=0; ready=0; data=PD; else if ready=0 then count=count+1; if count=5 then RDY=1; ready=1; countCLK,A0=a0,RW=rw,IRQ=irq,DOUT=d1,DIN=d2);u2: poc port map(clk=CLK,A0=a0,RW=rw,IRQ=irq,DOUT=d2,DIN=d1,RDY=rdy,TR=tr,PD=pd);u3: print port map(clk=CLK,RDY=rdy,TR=tr,PD=pd);end Behavioral;