现代逻辑设计英文试卷A-2014.doc

中国计量学院2013 ~ 2014学年第2学期
《 现代逻辑设计 》课程考试试卷（A）
开课二级学院：信息工程学院 ，考试时间： 2014 年 6 月 日 时
考试形式：闭卷□、开卷□，允许带 入场

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考生姓名： 学号： 专业： 班级：
题序
一
二
三
四
五
六
七
八
九
总分
得分

评卷人

一、 Fill in the blanks. (total 20/100, 2 for each blank)
1、Y = (sel)?(A+B):(A- B); if the value of sel is 1，the result of Y is A+B ,
otherwise the result of Y is A-B . The operator “? :” is called _条件运算符____.
2、The expand name of graphic file in Quartus II is pdf and the expand name
of waveform file is vwf .
3、The binary form of 8’h3f is ____8’b00111111_______________.
4、The general symbol of blocking statement is = . The general symbol of
non-blocking statement is <= .
5、Assumed A=2’b11, B=4’b1001, the value of “{A,B}” is ___6’b111001_ , the value of
“^b” is ___0_____.

二、Short-answer questions. (total 20/100)
1、 In Verilog HDL，what’s the meaning of “always@(posedge clk)” and
“always@(clk)”? (6/100)
第一个表示在时钟上升沿触发，第二个表示在时钟高电平触发。
一个是边沿敏感，一个是电平敏感。

2、 Finite State Machine (FSM) can be divided into two types according to the
generation of output values. What’s the difference between these two models?
(6/100)

根据输出信号产生方法的不同，状态机可分为两类：mealy和moore。
Moore型状态机的输出仅取决于当前状态，mealy型状态机的输出取决于当前状态和当前输入。

3．Please explain the structure of a Verilog module with examples.(8/100)

四个部分：模块申明、端口定义、数据类型定义、功能描述。

三、 Give the definition of the variables and constants. (total 12/100, 3 for each)
1、 Define an 8-bit bus of wire type named “ABUS”.

wire[7:0] ABUS;

2、 Define a 16-bit variable of reg type named “address”.

reg[15:0] address;

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3、 Define a parameter named “delay_time” which has the value of 8.

parameter delay_time=8;

4、 Define a memory with the word width of 32 and memory size of 128.

reg[31:0] memory[127:0];

四、Program comprehension. (total 16/100)
1、Please correct the program of an 4-bit comparator which has two 4-bit inputs a and b
and three outputs a_gt_b, a_eq_b and a_lt_b.（8/100）
module 4bit_comp(a, b, a_gt_b, a_eq_b, a_lt_b);
input[7:0] a, b;
output a_gt_b, a_eq_b, a_lt_b;
reg a_gt_b, a_eq_b, a_lt_b;
assign
a_gt_b=(a>b),
a_eq_b=(a=b),
a_lt_b=(a
input[2:0] a;
input en;
output[7:0] y __________________;
reg[7:0] y __________________;
always@(a or en)
if(en=1)
begin
case(a)____________;
3’b000: y=8’b11111110;
3’b001: y=8’b11111101;
3’b010: y=8’b11111011;
3’b011: y=8’b11110111;
___________ 11101111;____________;
3’b101: y=8’b11011111;
3’b110: y=8’b10111111;
3’b111: y=8’b01111111;
default: y=8’b11111111;
end
else y=8’b11111111;
endmodule

五、Programming (total 32/100）
1、According to the schematic diagram, please design a 2-1 MUX in structural style (using built-in primitives). ( 8/100)

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

2、Design a raising-edge triggered JK flip-flop with an asynchronous active-low reset.
(12/100)

3、Design a frequency divider of mod-12. (total 12/100)

中国计量学院2013 ~2014 学年第 2学期《现代逻辑设计》课程试卷（A）第 7 页 共 5 页