盛群单片机简介.pptx

2024/8/24Introduction of Holtek HT-46series MCU盛群半導體盛群半導體(股股)公司公司客戶技術服務處客戶技術服務處高克湘高克湘涂元崧涂元崧邱昱文邱昱文2024/8/24ContentFamily of A/D Type MCUi.Cost-Effective A/D type MCUii.A/D type MCUiii.A/D with LCD type MCUiv.A/D with VFD type MCUDetail of HT46R24i.Features of HT46R24ii.Block Diagramiii.Function Description(ROM,RAM,Interrupt,I/O,Timer,Buzzer,Oscillator,ADC,I2C,PWM,.)2024/8/24Cost-Effective A/D Type MCU2024/8/24A/D Type MCU2024/8/24A/D with LCD Type MCU2024/8/24Features of HT46R242024/8/24Block Diagram2024/8/24HT46X24 PIN ASSIGMENT2024/8/24Program ROM and Interrupt Vector2024/8/24RAM MAPPING2024/8/2463 InstructionsArithmeticlADD,SUBIncrement&DecrementlINC,INCA,DECLogic OperationlAND,OR,XORRotatelRR,RRC,RLData MovelMOVBit operationlSET,CLRTable ReadlTABRDC,TABRDLBranchlJMP,SZ,RET,RETIMiscellaneouslNOP,SWAP,HALT2024/8/24Arithmetic 2024/8/24Logic 2024/8/24Increment,Decrement,Rotate,Data Move,Bit Operation 2024/8/24Branch 2024/8/24Table Read,Miscellaneous 2024/8/24Indirect AddressingIndirect addressing Register:lIRA0,IRA1.Memory Pointers:lMP0,MP1.2024/8/24Status Register2024/8/24I/O Structure 2024/8/24InterruptInterrupt has priority issue.Once an interrupt subroutine is serviced,all the other interrupts will be block(by cleaning the EMI flag).After the subroutine set the“RETI”,the EMI will be set again.2024/8/24Interrupt control register2024/8/24Interrupt Scheme2024/8/24Timer/Event Counter 02024/8/24Timer/Event Counter 12024/8/24Timer Control Register 02024/8/24Timer Control Register 12024/8/243 modes available for the Timer/Counter 1.Timer Mode 2.Event Counter Mode 3.Pulse Width Mode 2024/8/244 steps to setup in the Timer Mode 1.Set to Timer Mode by writing 10 to TM1,TM0 2.Set the initial timer TMR value 3.Enable the corresponding interrupt by setting the ETI and EMI bit 4.Start the Timer by setting the TON bit of the TMRC 2024/8/245 steps to setup in the Even Counter Mode 1.Set to Event Counter Mode by writing 01 to TM1,TM0 2.Select TE=1 to count on the falling edge or TE=0 to count on the rising edge 3.Set the Timer initial value into TMR 4.Enable the corresponding interrupt by setting the ETI and EMI bits 5.Start the Timer by setting the TON bit in the TMRC register2024/8/245 steps to setup in the Pulse Width Measurement Mode 1.Set to Pulse Width Mode by writing 11 to TM1,TM0 2.Select TE=1 to measure a High Pulse Width and TE=0 to measure a Low Pulse Width 3.Set the Timer initial value,TMR,usually set to 0H for Pulse Width Measurements 4.Enable the corresponding interrupt by setting the ETI and EMI bits 5.Start the Timer by setting the TON bit in the TMRC 2024/8/24Programmable Frequency Divider(PFD)and BuzzerPFD is pin shared with PA3(selected via configuration optional).Clock source of PFD is come from timer0 or timer1 overflow signal(selected via configuration optional).PFD output is controlled by switch on/off PA3.2024/8/24Watchdog TimerThe watchdog timer is provided to prevent program uncontrollable.3 clock sources can be selected as watchdog timing source:(by configuration)lT1(fsys/4),32KHz RTC,WDT OSC output.lAt HALT,only WDT OSC or RTC oscillator is still running.2024/8/24Watchdog RegisterIf watchdog timeout,the system will be reset.The status bit“TO”will be set.There are two method of using software to clear watchdog timer(selected by configuration):lOne instruction:CLR WDTlTwo instruction:CLR WDT1,CLR WDT2 2024/8/24PWMPWM is Pulse Width Modulator.There are two modes 6+2 or 7+1 selected by configuration.User can change the duty cycle by softwarelby writing data to PWM0PWM3 special data register.PWM function can be controlled On/Off by software.lEnable PWM output:SET PD0lDisable PWM output:CLR PD0 2024/8/24PWM 6+2 Mode2024/8/24PWM 7+1 Mode2024/8/24Analog to Digital ConverterThe HT46R24 has a 10-bit ADC.ADC can be disabled by software.Max.4 or 8 channels can input to the ADC.lChannels set in ADCR by softwareADC channels are pin-shared with Port B.lAs ADC input or Port B set in ADCR by softwareInput range is from 0 to VDD.Min.ADC clock period is 1 us.ADC sampling time is 32 ADC clocks.ADC convert time is 76 ADC clocks.Max.INL 1 LSB.2024/8/24ADC Convert Data RegisterADRL/ADRH are two registers to store the ADC convert data.2024/8/24A/D Convert Control Register2024/8/24A/D Convert Clock Source Register2024/8/24A/D Convert Timing Diagram2024/8/24I2C Bus InterfaceI2C bus is a bidirectional 2-wire serial interface.lSCL:serial clock pin.lSDA:serial data pin.I2C output is of open drain.An external pull high resistor is needed.HT46 series I2C bus is only operates in Slave mode.For Master mode,user can implement by software.2024/8/24Data transfer on the I2C-bus2024/8/24I2C relative RegistersI2C Slave Address Register-HADRI2C Input/Output Data Register HDRI2C Control Register HCR.I2C Status Register HSR.2024/8/24HADR Register2024/8/24HDR Register2024/8/24HCR Register2024/8/24HSR Register2024/8/24I2C Bus CommunicationSTEP1lWrite the slave address of the microcontroller to the HADR.STEP2lSet the HEN(bit7 of HCR)to 1 to enable the I2C bus.STEP3lSet the EHI(bit2 of INTC1)to 1 to enable I2C interrupt2024/8/24I2C Bus ISR Flow Chart2024/8/24HALTThe system oscillator will be turned off.All of the I/O ports and RAM remain unchanged.The WDT will be cleared and resume counting if the WDT clock source is selected to come from the WDT oscillator.The PDF is set and the TO is cleared.2024/8/24How to wake up from HALT modeExternal ResetExternal InterruptFalling edge signal on port AWDT overflow2024/8/24RESETPower on resetReset pin resetLow Voltage ResetWDT reset2024/8/24Low Voltage Reset2024/8/24Register Initial Status(1)2024/8/24Register Initial Status(2)2024/8/24Register Initial Status(3)2024/8/24Application Circuit2024/8/24Configuration Options