基于单片机的步进电机电路控制设计英文文献及翻译.docx

The Stepper motor control circuit be based on Single chip microcomputer
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
Function characteristic
The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Description
VCC：Supply voltage.
GND：Ground.
Port 0：
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash programming and verification.

RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN
Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.

XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.

Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration
Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

Power-down Mode
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
Introduction
Stepper motors are electromagnetic incremental-motion devices which convert digital pulse inputs to analog angle outputs. Their inherent stepping ability allows for accurate position control without feedback. That is, they can track any step position in open-loop mode, consequently no feedback is needed to implement position control. Stepper motors deliver higher peak torque per unit weight than DC motors; in addition, they are brushless machines and therefore require less maintenance. All of these properties have made stepper motors a very attractive selection in many position and speed control systems, such as in computer hard disk drivers and printers, XY-tables, robot manipulators, etc.
Although stepper motors have many salient properties, they suffer from an oscillation or unstable phenomenon. This phenomenon severely restricts their open-loop dynamic performance and applicable area where high speed operation is needed. The oscillation usually occurs at stepping rates lower than 1000 pulse/s, and has been recognized as a mid-frequency instability or local instability [1], or a dynamic instability [2]. In addition, there is another kind of unstable phenomenon in stepper motors, that is, the motors usually lose synchronism at higher stepping rates, even though load torque is less than their pull-out torque. This phenomenon is identified as high-frequency instability in this paper, because it appears at much higher frequencies than the frequencies at which the mid-frequency oscillation occurs. The high-frequency instability has not been recognized as widely as mid-frequency instability, and there is not yet a method to evaluate it.
Mid-frequency oscillation has been recognized widely for a very long time, however, a complete understanding of it has not been well established. This can be attributed to the nonlinearity that dominates the oscillation phenomenon and is quite difficult to deal with.
384 L. Cao and H. M. Schwartz
Most researchers have analyzed it based on a linearized model [1]. Although in many cases, this kind of treatments is valid or useful, a treatment based on nonlinear theory is needed in order to give a better description on this complex phenomenon. For example, based on a linearized model one can only see that the motors turn to be locally unstable at some supply
frequencies, which does not give much insight into the observed oscillatory phenomenon. In fact, the oscillation cannot be assessed unless one uses nonlinear theory.
Therefore, it is significant to use developed mathematical theory on nonlinear dynamics to handle the oscillation or instability. It is worth noting that Taft and Gauthier [3], and Taft and Harned [4] used mathematical concepts such as limit cycles and separatrices in the analysis of oscillatory and unstable phenomena, and obtained some very instructive insights into the socalled loss of synchronous phenomenon. Nevertheless, there is still a lack of a comprehensive mathematical analysis in this kind of studies. In this paper a novel mathematical analysis is developed to analyze the oscillations and instability in stepper motors.
The first part of this paper discusses the stability analysis of stepper motors. It is shown that the mid-frequency oscillation can be characterized as a bifurcation phenomenon (Hopf bifurcation) of nonlinear systems. One of contributions of this paper is to relate the midfrequency oscillation to Hopf bifurcation, thereby, the existence of the oscillation is proved
theoretically by Hopf theory. High-frequency instability is also discussed in detail, and a novel quantity is introduced to evaluate high-frequency stability. This quantity is very easy
to calculate, and can be used as a criteria to predict the onset of the high-frequency instability. Experimental results on a real motor show the efficiency of this analytical tool.
The second part of this paper discusses stabilizing control of stepper motors through feedback. Several authors have shown that by modulating the supply frequency [5], the midfrequency
instability can be improved. In particular, Pickup and Russell [6, 7] have presented a detailed analysis on the frequency modulation method. In their analysis, Jacobi series was used to solve a ordinary differential equation, and a set of nonlinear algebraic equations had to be solved numerically. In addition, their analysis is undertaken for a two-phase motor, and therefore, their conclusions cannot applied directly to our situation, where a three-phase motor will be considered. Here, we give a more elegant analysis for stabilizing stepper motors, where no complex mathematical manipulation is needed. In this analysis, a d–q model of stepper motors is used. Because two-phase motors and three-phase motors have the same q–d model and therefore, the analysis is valid for both two-phase and three-phase motors. Up to date, it is only recognized that the modulation method is needed to suppress the midfrequency oscillation. In this paper, it is shown that this method is not only valid to improve mid-frequency stability, but also effective to improve high-frequency stability.
2. Dynamic Model of Stepper Motors
The stepper motor considered in this paper consists of a salient stator with two-phase or threephase windings, and a permanent-magnet rotor. A simplified schematic of a three-phase motor with one pole-pair is shown in Figure 1. The stepper motor is usually fed by a voltage-source inverter, which is controlled by a sequence of pulses and produces square-wave voltages. This
motor operates essentially on the same principle as that of synchronous motors. One of major operating manner for stepper motors is that supplying voltage is kept constant and frequency
of pulses is changed at a very wide range. Under this operating condition, oscillation and instability problems usually arise.

Figure 1. Schematic model of a three-phase stepper motor
A mathematical model for a three-phase stepper motor is established using q–d framereference transformation. The voltage equations for three-phase windings are given by
va = Ria + L*dia /dt − M*dib/dt − M*dic/dt + dλpma/dt ,
vb = Rib + L*dib/dt − M*dia/dt − M*dic/dt + dλpmb/dt ,
vc = Ric + L*dic/dt − M*dia/dt − M*dib/dt + dλpmc/dt ,
where R and L are the resistance and inductance of the phase windings, and M is the mutual inductance between the phase windings. _pma, _pmb and _pmc are the flux-linkages of the
phases due to the permanent magnet, and can be assumed to be sinusoid functions of rotor position _ as follow
λpma = λ1 sin(Nθ),
λpmb = λ1 sin(Nθ − 2 π/3),
λpmc = λ1 sin(Nθ - 2 π/3),
where N is number of rotor teeth. The nonlinearity emphasized in this paper is represented by the above equations, that is, the flux-li