VHDL数字钟设计方案报告.doc

VHDL数字钟设计汇报一. 数字钟总体设计方案：1.1设计目标正确显示时、分、秒；可手动校时，能分别进行时、分校正； 整点报时功效；1.2设计思绪数字钟设计模块包含：分频器、去抖动电路、校时电路、“时、分、秒”计数器、校时闪烁电路、整点报时和译码显示电路。每一个功效模块作为一个实体单独进行设计，最终再用VHDL例化语句将各个模块进行整合，生成顶层实体top。 该数字钟能够实现3个功效：计时功效、设置时间功效和报时功效。二数字钟模块细节 2.1 分频器（fenpin） 本系统共需3种频率时钟信号（1024Hz、512Hz、1Hz）。为降低输入引脚，本系统采取分频模块，只需由外部提供1024Hz基按时钟信号，其它三种频率时钟信号由分频模块得到。 分频原理：为以1024Hz基按时钟经1024分频得到512Hz,1Hz频率时钟信号。 分频器管脚 代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;entity fenpin is port(clk1024:in std_logic; clk1,clk512:out std_logic );end fenpin ; architecture cml of fenpin is begin process (clk1024) variable count1: integer range 0 to 512; variable q1: std_logic; begin if clk1024 event and clk1024=1 then if count1=512 thenq1:=not q1; count1:=0; else count1:=count1+1; end if; end if; clk1=q1; end process; process(clk1024) variable count512: integer range 0 to 1; variable q512: std_logic; begin if clk1024 event and clk1024=1 then if count512=1 then q512:=not q512; count512:=0; else count512:=count512+1; end if; end if; clk512=q512; end process;end cml; 22 校时电路（jiaoshi）本模块要实现功效是：正常计时、校时、校分在每个状态下全部会产生不一样控制信号实现对应功效。校时管脚图代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jiaoshi is port(rst,rvs,select_rvs,mtime,mclkin,hclkin:in std_logic; hclkout,mclkout:out std_logic ); end jiaoshi; architecture cml of jiaoshi is signal h_m:std_logic; begin p1:process(rst,rvs,hclkin,mclkin,h_m,mtime) begin if rst=0 then null; elsif rvs=1 then hclkout=hclkin; mclkout=mCLKin; elsif h_m=0 then hclkout=hclkin; mclkout=mtime; else hclkout=mtime;mclkout=mclkin; end if; end process;p2:process(select_rvs) begin if select_rvsevent and select_rvs=1 then h_m=not h_m; end if; end process ; end cml;管脚图仿真图2.3 时计数器（hour）分计数器(mine)秒计数器(second) 时计数器管脚图 时代码： library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour isport(rst,hclk:in std_logic; hour0,hour1:buffer std_logic_vector(3 downto 0 ) );end hour;architecture cml of hour is beginprocess(rst,hclk,hour0,hour1) begin if rst=0 then hour0=0000; hour1=0000; elsif hclkevent and hclk=1 then if hour0=0011 and hour1=0010 then hour0=0000; hour1=0000; elsif hour0=1001 then hour0=0000; hour1=hour1+1; else hour0=hour0+1; end if; end if; end process ; end cml; 分计数器管脚图分代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mine isport(rst,mclk:in std_logic; mco:out std_logic; min0,min1:buffer std_logic_vector(3 downto 0 ) );end mine;architecture cml of mine issignal min0_t,min1_t:std_logic_vector(3 downto 0 ); beginprocess(rst,mclk,min0,min1) begin if rst=0 then min0=0000; min1=0000; elsif mclkevent and mclk=1 then if min0=0101 and min1=1001 then min0=0000; min1=0000; mco=1; elsif min0=0010 and min0=1001 then min1=0011; min0=0000; mco=0;elsif min0=1001 then min1=min1+1; min0=0000; else min0=min0+1; end if; end if; end process ; end cml; 秒计数器管脚图 秒代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport(rst,sclk:in std_logic; sco:out std_logic; sec0,sec1:buffer std_logic_vector(3 downto 0 ) );end second;architecture cml of second issignal sec0_t,sec1_t:std_logic_vector(3 downto 0 ); beginprocess(rst,sclk,sec0,sec1) begin if rst=0 thensec0=0000; sec1=0000; elsif sclkevent and sclk=1 then if sec0=0101 and sec1=1001 then sec0=0000; sec1=0000; sco=1; elsif sec0=0010 and sec0=1001 then sec1=0011; sec0=0000; sco=0;elsif sec0=1001 then sec1=sec1+1; sec0=0000; else sec0=sec0+1; end if; end if; end process ; end cml; 2.4 校时闪烁电路（flashnjiaoshi）假如正在进行校时，flashjiaoshi将实现使目前正在校时项（小时或分钟）以1Hz频率闪烁，方便于操知道正在被校正。 校时闪烁电路管脚图代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity flashjiaoshi isport(rst,sclk,rvs,select_rvs:in std_logic; hour0in,hour1in,min0in,min1in:in std_logic_vector(3 downto 0 ); hour0out,hour1out,min0out,min1out :out std_logic_vector(3 downto 0 ) );end flashjiaoshi;architecture cml of flashjiaoshi is signal h_m:std_logic; begin p1:process(rst,sclk,rvs,hour0in,hour1in,min0in,min1in,h_m) begin if rst=0 then null; elsif rvs=1 then hour0out=hour0in;hour1out=hour1in;min0out=min0in;min1out=min1in; elsif h_m=0 then hour0out=hour0in; hour1out=hour1in; if sclk=1 then min0out=min0in; min1out=min1in; else min0out=1111; min1out=1111; end if;else min0out=min0in; min1out=min1in;IF sCLK=1 then hour0out=hour0in; hour1out=hour1in;else hour0out=1111; hour1out=1111;end if;end if;end process p1;p2:process(select_rvs) beginif select_rvsevent and select_rvs=1 then h_m=not h_m;end if;end process p2;end cml; 2.5 整点报时电路 整点报时管脚图 代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity baoshi isport( clk1024,clk512 : in std_logic; min0,min1 , sec0,sec1 : in std_logic_vector (3 downto 0); speak : out std_logic); end baoshi;architecture cml of baoshi is beginspeakdata=h1;select_sigdata=h0;select_sigdata=m1;select_sigdata=m0;select_sigdata=s1;select_sigdata=s0;select_sigdata=1000;select_sig=111111; end case;if order=101 then order=000;else orderseg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7 seg7 clk1024,clk512=scanCLKSig,clk1=secCLKSig);U2: jiaoshi PORT MAP(rst=reset, rvs=key, select_rvs=keyin(0), mtime=keyin(1), hclkin=hCLKSig0,mclkin=mCLKSig0,hclkout=hCLKSig1,mclkout=mCLKSig1); U3:hour PORT MAP(rst=reset, hCLK=hCLKSig1, hour1=hour1Sig0, hour0=hour0Sig0); U4: minute PORT MAP(rst=reset, mclk=mCLKSig1, mco=hCLKSig0, min1=min1Sig0, min0=min0Sig0); U5: second PORT MAP(rst=reset, sCLK=secCLKSig, sco=mCLKSig0, sec1=sec1Sig, sec0=sec0Sig); U6: flashjiaoshi PORT MAP(rst=reset, sclk=secCLKSig, rvs=key, select_rvs=keyin(0), hour1in=hour1Sig0, hour0in=hour0Sig0, min1in=min1Sig0, min0in=min0Sig0, hour1out=hour1Sig1, hour0out=hour0Sig1, min1out=min1Sig1, min0out=min0Sig1); U7: xianshi PORT MAP(clk512=scanCLKSig, h1=hour1Sig1, h0=hour0Sig1, m1=min1Sig1, m0=min0Sig1, s1=sec1Sig, s0=sec0Sig, seg7=seg7out, select_sig=select_sigout); u8:baoshi PORT MAP(clk1024=clk1024,clk512=scanCLKSig,sec1=sec1Sig,sec0=sec0Sig, min1=min1Sig0,min0=min0Sig0,speak=speak); END cml;