dds论文外文翻译-关于直接数字频率合成器本科毕业论文.doc

All About Direct Digital Synthesis
What is Direct Digital Synthesis?
Direct digital synthesis (DDS) is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power.
Why would one use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies?
The ability to accurately produce and control waveforms of various frequencies and profiles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations.

Figure 1. The AD9833-a one-chip waveform generator.
Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and industrial applications because single-chip IC devices can generate programmable analog output waveforms simply and with high resolution and accuracy.
Furthermore, the continual improvements in both process technolog y and design have resulted in cost and power consumption levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator (Figure 1), operating at 5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts.

What are the main benefits of using a DDS?
DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an extremely attractive solution—preferable to less-flexible solutions comprising aggregations of discrete elements.
What kind of outputs can I generate with a typical DDS device?

Figure 2. Square-, triangular-, and sinusoidal outputs from a DDS.
DDS devices are not limited to purely sinusoidal outputs. Figure 2 shows the square-, triangular-, and sinusoidal outputs available from an AD9833.
How does a DDS device create a sine wave?
Here’s a breakdown of the internal circuitry of a DDS device: its main components are a phase accumulator, a means of phase-to-amplitude conversion (often a sine look-up table), and a DAC. These blocks are represented in Figure 3.

Figure 3. Components of a direct digital synthesizer.
A DDS produces a sine wave at a given frequency. The frequency depends on two variables, the reference-clock frequency and the binar y number programmed into the frequency register (tuning word).
The binary number in the frequency register provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up table, which outputs the digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The DAC in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value (the phase increment—which is determined by the binary number) is added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform.
What do you mean by a complete DDS?
The integration of a D/A converter and a DDS onto a single chip is commonly known as a complete DDS solution, a property common to all DDS devices from ADI.
Let’s talk some more about the phase accumulator. How does it work?

Figure 4. Digital phase wheel.
Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 2.The digital implementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS implementation.
To understand this basic function, visualize the sine-wave oscillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to the equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visualize that the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel, at a constant speed, results in one complete cycle of the output sine wave. The phase accumulator provides the equally spaced angular values accompanying the vector’s linear rotation around the phase wheel. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave.
The phase accumulator is actually a modulo- M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binary-coded input word (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28-bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 reference-clock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 reference-clock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:

where:
fOUT = output frequency of the DDS
M = binary tuning word
fC = internal reference clock frequency (system clock)
n = length of the phase accumulator, in bits
Changes to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked loop.
As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output.
When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp.
Then how is that linear output translated into a sine wave?
A phase -to - amplitude lookup table is used to convert the phaseaccumulator’s instantaneous output value (28 bits for AD9833)—with unneeded less-significant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10 -bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in
Figure 5.

Figure 5. Signal flow through the DDS architecture.

关于直接数字频率合成器
什么是直接数字频率合成器？
直接数字频率合成器（DDS）是一种通过产生一个以数字形式时变的信号，然后执行由数字至模拟转换的方法。由于DDS设备的操作主要是数字的，它可以提供快速解决输出频率之间切换，优点是具有精细的频率以及运行频率范围广泛。由于设计方面和工艺技术的进步，如今DDS器件已变得非常紧凑而且功率非常小。
为什么要使用直接数字频率合成器（DDS）？难道没有其它方法使不同频率和配置文件能够很容易地产生频率？
能够准确地产生和控制波形已经成为一些行业的主要要求。无论是提供低相位噪声的杂散性能良好的可变频率通信，还是只需在生成的频率上激活工业或生物医学检测设备的应用程序，成本低是重要的设计考虑。
设计师以相位锁定回路（PLL）为基础，需要非常高的频率合成技术，以动态规划的数字到模拟的转换器（DAC）来产生许多可能产生的频率，但DDS技术迅速获得了解决频率（或波形）产生和工业应用要求的方法，因为单芯片集成电路器件可以产生简单的可编程的模拟输出高分辨率和准确性的波形。
此外，在这两个过程中不断改进技术和设计，使成本和功耗水平前所未有的低。例如AD9833，一个基于DDS的可编程波形发生器（图1），工作电压5.5V与25MHz的时钟，消耗的最大功率为30mW。

图1 AD9833波形发生器

使用DDS有什么主要好处？
对DDS的AD9833器件进行编程，如通过一个高速串行外设接口（SPI），而且只需要一个外部时钟来生成简单的正弦波。DDS器件现已可以产生从1到400MHz的频率，（时钟基于103MHz兆赫）。电源效益低，成本低，包装单小，加上其固有的优良性能，并能够以数字形式（和重新编程）输出波形使DDS器件是极具吸引力的解决方案，相比不太灵活的包括分子聚合离散在内的解决方案。
一个典型的DDS的设备可以产出什么样的输出？
DDS器件不仅限于纯粹的正弦波输出。图2显示了方波、三角波和正弦波输出。

图2 DDS输出的矩形波-三角波-正弦波
如何使用DDS的设备创建一个正弦波？
这里有一个DDS的内部电路：其主要成分是相位累加器，振幅转换（通常是正弦查找）和一个DAC。这些模块的代表图如图3。

图3 组件的直接数字合成器

DDS产生一个特定频率的正弦波。它的频率取决于两个变量，参考时钟频率和（控制字）数字编程的频率。
二进制数的频率主要输入到相位累加器。在使用正弦查找表时，用相位累加器计算一个阶段（角）的地址查找表，输出幅度的数字值对应相位角的正弦。反过来，DAC把这个数字转换为相应值的模拟电压或电流。要生成一个固定频率的正弦波，恒定值（相位增量，这是由二进制数决定）被添加到时钟周期的相位累加器。如果相位增量大，相位累加器会迅速通过正弦查找表，从而产生高频率的正弦波。如果相位增量小，相位累加器将采取更多的步骤，因而产生较慢的波形。
完整的DDS是什么意思？
D/A转换器和一个DDS的单一芯片的整合通常被称为一个完整的DDS的解决方案，ADI公司的普通性质DDS。让我们说些有关累加器的知识。它是如何工作的？连续时间正弦信号的角度范围内有一个重复的阶段0至2。数字的实施没有什么不同，该计数器可以把相位累加器作为DDS的功能来执行。

图4 数字相位轮
为了理解这一点的基本功能，将可视化的正弦波振荡作为一个阶段轮围绕旋转圆向量（见图4）。每个阶段轮指向对应的等效点1波周期的正弦。由于矢量旋转的轮子，形象化的角度的正弦值产生相应的正弦波。一个车轮周围的相速度向量，为一个常数，正弦波输出结果为一个完整周期。相位累加器提供等距相角值随车轮周围的向量线性旋转。相位累加器对应于点的波周期输出的正弦。
相位累加器实际上是一个模- M的计数器，每次收到一个时钟脉冲其存储的数量递增。递增幅度取决于输入字（米）。这个字形成相位步长之间的参考，它有效地设置跳过多少分左右相轮。规模越大的跳跃，相位累加器以越快的速度溢出，且其周期相当于一个正弦波。该轮在数字离散相点中，取决于分辨率的相位累加器（n），这决定了DDS的调谐。对于一个n = 28位相位累加器，1 ... 0001 M值的0000会导致相位累加器溢出后228参考时钟周期（增量）。如果M值更改为0111 ... 1111，相位累加器溢出后，将只有2参考时钟周期（取决于奈奎斯特最低要求）。这种关系是发生在基本调整方程DDS的结构为：

其中：FOUT是DDS的输出频率
M是频率控制字的二进制
fC是内部参考时钟频率（系统时钟）
n是每组长度的相位累加器位，
M的值发生变化导致输出频率的变化。无回路的建立时间发生在一个循环锁相内。由于输出频率的增加，减少样本周期数。
由于抽样理论决定了至少两个周期，每样都需要重建的输出波形，基本的DDS输出频率是fC/2。
然而，对于实际应用中，输出频率是有限的，在一定程度改善波形质量的重建，并允许滤波输出。当产生一个恒定的频率，相位输出线性增加，因此模拟波形生成本身就是一个斜坡。
试问，线性输出波形怎样转化为正弦波？
A相方法-振幅查找表用于转换相位累加器的瞬时输出值（28比特AD9833）将正弦波振幅信息，提交（10位）到D/A转换器。DDS的结构充分利用了正弦波对称的性质和利用的一个映射逻辑合成一个完整周期的正弦波。该相位对振幅查找表其余数据通过阅读然后再向前，这形象地显示在图5。

图5 流过DDS的信号

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