调制直接数字频率合成器系统(中英文).doc

中文翻译1：调制直接数字频率合成器系统DDS（直接数字频率合成）总的介绍：在探讨许多复杂的相位连续的调制技术中，对模拟电路中输出波形的控制已经越来越困难。在这些设计中，使用非线性数字式设计消去电路板需要的调整额外输出和温度。一种适合这个目标的数字式设计就是直接数字频率合成器（DDS）。一个DDS系统仅仅使用一个恒定参考时钟输入和将该时钟分解为指定的量化数位频率输出或者对参考时钟频率取样。这种形式频率控制使得DDS系统成为需要精确频率扫描比如雷达尖叫声或者快速频率计数器的理想系统。根据数字输入控制字以控制输出频率，DDS系统可以用来当作一个允许精确频率连续改变相位的锁相环（PLL）。根据后面的说明，我们知道DDS系统还可以使用输入数字相位控制字来控制输出载波的相位。用数字式控制载波相位，很容易产生一个高频谱密度的相位调制载波。本文主旨是给读者一个基本的DDS设计和寄生输出响应的知识。本文将展示一个运行于45MHz的快速现场可编辑逻辑器件。DDS系统框图：一个基本的DDS系统包括一个数字振荡器（NCO）用来产生输出载波，和一个数模转换器（DAC）用来将从NCO过来的数字式正弦曲线字产生一个抽样的模拟载波。因为DAC的输出是根据参考时钟频率的抽样，通常用一个圆滑波形的低通滤波器来消除混叠成分。图1是一个典型的DDS系统设计图表。根据输入的参考时钟抽样经过NCO来产生输出载波。NCO的基本构成是一个相位累加器和一个正弦ROM查找表。通过增加NCO的载波相位调制的输出能力可以提高DDS系统的设计。图2是一个详细的展示可变相位调制器的典型NCO设计图表。图1 典型的DDS系统图2 典型的NCO设计为了更好的理解NCO设计的各种功能，首先考虑仅包括一个相位累加器和一个正弦ROM查找表的基本NCO设计。与欧拉公式（）图解比较就能最好地去理解这两个表的NCO设计的功能。欧拉公式的图解如图3所示，是一个单位向量绕着实轴和虚平面的中心以W rad/s的速度转圈。这个频率控制字是最后一个抽样相位值通过一个N位加法器的连续地累加而成。加法器的输出是参考抽样时钟通过一个N位寄存器的抽样。当累加器达到N位最大值的时候，累加器翻转然后继续。画出抽样累加器的值对时间的关系正如图3所示的一个锯齿波。这里Troll是旋转的相位累加量，Fout是DDS系统输出频率，Fclk是时钟采样频率，FW(N-1:0)是输入的总量，FW(N-1:0)/2N是输入间隔量。然后相位累加器的抽样输出用来在一个正弦量化值表里进行查找。抽样相位到正弦量化的转化可以看作是真实的或者虚拟的成分及时地影射。因为相位累加器的比特位数决定了频率调整的步进，一个典型的相位累加器的大小是24到32位。由于正弦ROM表的大小是跟寻址范围直接成比例的，因此，不是所有相位累加器的24或32位都用来作为正弦ROM表的地址。仅是相位累加器的高Y（YN）位是用来作为正弦ROM表的地址，Y通常不必要等于正弦ROM表的输出量位D。图3 欧拉公式表征图解DDS设计事项因为一个NCO输出基于一个数字表示的相位和正弦波量化形式的载波，所以设计者可以完全的控制输出载波的频率、相位和幅度。通过加入一个相位端口和一个相位加法器到一个基本的NCO设计中，NCO的输出载波当M等于相位端口数和M小于或等于Y（用来作为正弦ROM表的地址位数）时可以被M矩阵相位调制。假如系统设计需要幅度调制如QAM，可以加入一个量化端口来调整正弦ROM表的输出。注意到这个端口没有在图2里表示出来以及这个特色没有在简单的快速逻辑FPGA设计中论证。最后，频率是调制是一个基本的NCO设计给出的。因为频率控制字是跟抽样时钟是同步装载到DDS的，频率的转化是相位连续的。 虽然DDS系统给设计者完全地控制复杂的调制合成，但是在一个非线性数字格式的正弦相位和量级的表示却是复杂的新设计。在取样任何的连续时间信号时，必须考虑取样原理和量子化误差。 为了理解DDS系统中取样理论的效果，最好看一下时间和频率域的DDS合成过程。就象上面规定的，通过以指定的速率累积的形式由NCO产生一个正弦波然后用一个相位的值来定位一个正弦调制ROM表的值。因此，NCO本质上用一个正弦波和用NCO的上升或下降沿输出参考取样时钟对其取样。图4表示在时间和频率域里NCO的处理。注意到这个表示并非量子化假设。 基于频率控制字的装载，NCO在一个时期内提供一批幅度的输出值。这个正弦曲线的频率域表示在指定的频率里是一个推动的作用。NCO在NCO参考时钟速率下输出这个正弦曲线的离散数字取样。在时间域里，NCO输出是一个取样时钟边缘闸门乘于正弦波形式产生的一个推动序列正弦振幅的作用。在频率域里，参考时钟的取样产生一系列在K倍的NCO时钟频率脉冲（当K=.-1，2，1，2.）。当在时间域里取样时钟乘于正弦曲线，正弦曲线频率域成分和取样时钟需要卷积来产生NCO输出频率域表示的NCO输出。 频率域的结果是在正弦曲线基本频率的脉冲作用和别的脉冲作用发生在K倍的NCO时钟频率加上或减去基本频率。基本的和别的成分发生在： K*Fclk - Fout K*Fclk + Fout 当K = . -1, 0 , 1, 2 . 和 K = 0是NCO正弦曲线基本频率。 Fout是指定的NCO正弦曲线输出频率Fclk是NCO参考时钟频率图4 NCO输出的时域和频域表示 DDS系统中的DAC提取NCO的输出值并转化他们的值为模拟电压。图4显示出时间和频率域DAC过程开始于NCO的输出的表示。DAC输出是一个抽样和保持那些NCO数字幅度控制字和转换那些值为一个模拟电压和保持那些值为一个抽样时钟周期的电路。DAC过程的时域结构是NCO抽样输出值和一个抽样周期脉冲的卷积。抽样脉冲的频率域结构是一个sin(x)/x功能和在抽样时钟频率的第一个零。因为时域是卷积的，频率域就是相当于相乘。这个乘法过程使得NCO输出有一个sin(x)/x包络。这个在DAC输出的衰减在下面计算出来而且一个抽样输出频谱如图5所示：图5 DAC输出的时域和频域表示Atten(F) = 20log(sin(pF/Fclk)/pF/Fclk)当F是输出频率，Fclk是抽样时钟频率。 根据取样理论，实际的值量子化为数字形式必须考虑一个DDS系统的性能分析。一个DDS系统的假的响应是主要由两个量子化参量确定的。这些参量是相位累加器的相位量子化和ROM正弦曲线表和DAC的量子化量级。 如上所示，相位累加器只有高Y比特是用来寻址ROM表。值得注意的是，仅用高Y位引入一个相位截短。当一个频率控制字包含一个非零的值在低（N-Y-1：0）位是装载到DDS系统的，低非零位累加到高Y位和使得产生一个相位截短。相位的截短出现的频率可以根据以下计算：Ftrunc = FW(N-Y-1:0)/2N-Y * Fclk.一个相位的截短会周期性（以Ftrunc速率）相位调制输出载波提前2/来补偿频率控制字间隔多于。相位的跳转由相位截短位累加在基波周围产生突刺。这些突刺位于基频的正和负截短频率，突刺的大小是20log()dBc。一个相位截短突刺输出的例子如图5所示。在一个典型的NCO设计里，正弦ROM表会保持一个1/4正弦波（0，/2）的量级。ROM表是通过把所有可能的相位值地址和映射到实际正弦波大小的近似D比特来产生的。因此，最大的输出误差为-1/2 LSB（假设当突刺为-20log()dBc的最坏情况时）。 类似于NCO的ROM表，一个DAC也同样是这样量子化数字值为模拟值的。一个DAC输出的模拟电压取决于输入的数字值。当设计NCO正弦ROM表时，一种方法是根据经验好于通过理解ROM表和DAC之间的交互作用而在DAC线性得出一些数据。DAC的量化曲线数字输入对应模拟输出的DAC量化曲线可以看作是理想线性的。微分线性和积分线性这两个线性参数通常是用来衡量DAC性能。微分线性是指输出的步进大小为比特到比特。一个DAC必须编码一个最大的1LSB微分线性。当输入码增加，DAC的输出必须相应增加。假如DAC电压的增加不是对应于一个增加的输入数字值，可以说DAC是缺码的。因此，一个有大于1LSB微分线性的10比特DAC可以精确到9或者更小的比特。精确输出的比特数量会导致DDS当dl是微分线性的比特数量时的虚假的性能-20log()。积分线性是一个DAC的总的线性性能对一个理想的线性直线的一个衡量。那条直线图当DC偏置可能是DAC的最大或者最小时可以看作“最好的直线”，或者那条直线可以穿过输出的最大和最小值的结束点。超出输出范围时一个DAC会有一个特有的弯曲特性曲线。根据曲线的形状和对称度（半个DAC输出的周期对称），就可以产生DDS基本输出频率的输出“和”。当这些“和”接近和超过耐奎斯特频率，Fclk/2，这些“和”就成为样本之下和反映到重要的边带，0到Fclk/2。这个问题可以通过设置NCO的输出到Fclk/4加上一个轻微的偏移量来说明。第三谐波将倒减去3折轻微的偏移量基波和二次谐波相交耐奎斯特频率的2折偏移量，留下一个反射图象在边缘。一个典型的频率建立的过程如图5。另外DAC将产生谐波失真的性质是任意输出波形的对称的分解，例如一个不同的上升和下降时间。这些性质通常可以由电路板的DAC的外部元件来修正，例如一个RF变压器，电路板设计问题，衰减点等。英文原文1：Modulating Direct Digital Synthesizer System DDS OverviewIn the pursuit of more complex phase continuous modulation techniques,the control of the output waveform becomes increasingly more difficult with analog circuitry. In these designs, using a non-linear digital design eliminates the need for circuit board adjustments over yield and temperature. A digital design that meets these goals is a Direct Digital Synthesizer DDS. A DDS system simply takes a constant reference clock input and divides it down a to a specified output frequency digitally quantized or sampled at the reference clock frequency. This form of frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar chirps or fast frequency hoppers. With control of the frequency output derived from the digital input word, DDS systems can be used as a PLL allowing precise frequency changes phase continuously. As will be shown, DDS systems can also be designed to control the phase of the output carrier using a digital phase word input. With digital control over the carrier phase, a high spectral density phase modulated carrier can easily be generated.This article is intended to give the reader a basic understanding of a DDS design, and an understanding of the spurious output response. This article will also present a sample design running at 45MHz in a high speed field programmable gate array from QuickLogic.DDS Block DiagramA basic DDS system consists of a numerically controlled oscillator (NCO) used to generate the output carrier wave, and a digital to analog converter (DAC) used to take the digital sinusoidal word from the NCO and generate a sampled analog carrier. Since the DAC output is sampled at the reference clock frequency, a wave form smoothing low pass filter is typically used to eliminate alias components. Figure 1 is a basic block diagram of a typical DDS system design.The generation of the output carrier from the reference sample clock input is performed by the NCO. The basic components of the NCO are a phase accumulator and a sinusoidal ROM lookup table. An optional phase modulator can also be include in the NCO design. This phase modulator will add phase offset to the output of the phase accumulator just before the ROM lookup table. This will enhance the DDS system design by adding the capabilities to phase modulate the carrier output of the NCO. Figure 2 is a detailed block diagram of a typical NCO design showing the optional phase modulator.FIGURE 1: Typical DDS System.FIGURE 2: Typical NCO Design.To better understand the functions of the NCO design, first consider the basic NCO design which includes only a phase accumulator and a sinusoidal ROM lookup table. The function of these two blocks of the NCO design are best understood when compared to the graphical representation of Eulers formula . The graphical representation of Eulers formula, as shown in Figure 3, is a unit vector rotating around the center axis of the real and imaginary plane at a velocity of rad/s. Plotting the imaginary component versus time projects a sine wave while plotting the real component versus time projects a cosine wave. The phase accumulator of the NCO is analogous, or could be considered, the generator of the angular velocity component rad/s. The phase accumulator is loaded, synchronous to the reference sample clock, with an N bit frequency word.This frequency word is continuously accumulated with the last sampled phase value by an N bit adder. The output of the adder is sampled at the reference sample clock by an N bit register. When the accumulator reaches the N bit maximum value, the accumulator rolls over and continues. Plotting the sampled accumulator values versus time produces a saw tooth wave form as shown below in Figure 3.Where Troll is the phase accumulator rollover period Fout is the DDS system output carrier frequency F clk is the reference sample clock frequency FW(N-1:0) is the frequency word input value and the frequency granularity is FW(N-1:0)/2NThe sampled output of the phase accumulator is then used to address a ROM lookup table of sinusoidal magnitude values. This conversion of the sampled phase to a sinusoidal magnitude is analogous to the projection of the real or imaginary component in time. Since the number of bits used by the phase accumulator determines the granularity of the frequency adjustment steps, a typical phase accumulator size is 24 to 32 bits. Since the size of the sinusoidal ROM table is directly proportional to the addressing range, not all 24 or 32 bits of the phase accumulator are used to address the ROM sinusoidal table. Only the upper Y bits of the phase accumulator are used to address the sinusoidal ROM table, where Y N bits and Y is typically but not necessarily equal to D, and D is the number of output magnitude bits from the sinusoidal ROM table.FIGURE 3 Eulers Equation Represented GraphicallyDDS Design ConsiderationsSince an NCO outputs a carrier based on a digital representation of the phase and magnitude of the sinusoidal wave form, designers have complete control over frequency, phase, and even amplitude of the output carrier By adding a phase port and a phase adder to the basic NCO design, the output carrier of the NCO can be M array phase modulated where M equals the number of phase port bits and where M is less than or equal to the Y number of bits used to address the sinusoidal ROM table. For system designs that require amplitude modulation such as QAM, a magnitude port can be added to adjust the sinusoidal ROM table output. Note that this port is not shown in Figure 2 and that this feature is not demonstrated in the sample QuickLogic FPGA design. Finally, frequency modulation is a given with the basic NCO design. The frequency port can directly adjust the carrier output frequency. Since frequency words are loaded into the DDS synchronous to the sample clock, frequency changes are phase continuous.Although DDS systems give the designer complete control of complex modulation synthesis, the representation of sinusoidal phase and magnitude in a non-linear digital format introduces new design complexities. In sampling any continuous-time signal, one must consider the sampling theory and quantization error.To understand the effects of the sampling theory on a DDS system, it is best to look at the DDS synthesis processes in both the time and frequency domain. As stated above, the NCO generates a sinusoidal wave form by accumulating the phase at a specified rate and then uses the phase value to address a ROM table of sinusoidal amplitude values. Thus, the NCO is essentially taking a sinusoidal wave form and sampling it with the rising or falling edge of the NCO input reference sampling clock. Figure 4 shows the time and frequency domain of the NCO processing. Note that this representation does not assume quantization.Based on the loaded frequency word, the NCO produces a set of amplitude output values at a set period. The frequency domain representation of this sinusoid is an impulse function at the specified frequency. The NCO, however, outputs discrete digital samples of this sinusoid at the NCO reference clock rate. In the time domain, the NCO output is a function of the sampling clock edge strobes multiplied by the sinusoid wave form producing a train of impulses at the sinusoid amplitude. In the frequency domain, the sampling strobes of the reference clock produce a train of impulses at frequencies of K times the NCO clock frequency where K = . - 1, 0, 1, 2 . Since the sampling clock was multiplied by the sinusoid in the time domain, the frequency domain components of the sinusoid and the sampling clock need to be convolved to produce the frequency domain representation of the NCO output.The frequency domain results are the impulse function at the fundamental frequency of the sinusoid and the alias impulse functions occurring at K times the NCO clock frequency plus or minus the fundamental frequency. The fundamental and alias component occur at:K*Fclk FoutK*Fclk + FoutWhere K = . -1, 0 , 1, 2 . and K = 0 is the NCO sinusoid fundamental frequency Fout is the specified NCO sinusoid output frequency Fclk is the NCO reference clock frequencyFIGURE 4 NCO Output Representation Time and Frequency DomainThe DAC of the DDS system takes the NCO output values and translates these values into analog voltages. Figure 4 shows the time and frequency domain representations of the DAC processing starting with the NCO output. The DAC output is a sample and hold circuit that takes the NCO digital amplitude words and converts the value into an analog voltage and holds the value for one sample clock period. The time domain plot of the DAC processing is the convolution of the NCO sampled output values with a pulse of one sample clock period. The frequency domain plot of the sampling pulse is a sin(x)/x function with the first null at the sample clock frequency. Since the time domain was convolved, the frequency domain is multiplied. This multiplication dampens the NCO output with the sin(x)/x envelope. This attenuation at the DAC output can be calculated as follows and a sample output spectrum is shown in Figure 5:FIGURE 5: DAC Output Representation in Time and Frequency DomainAtten(F) = 20log(sin(pF/Fclk)/pF/Fclk)Where F is the output frequencyFclk is the sample clock frequencyAside from the sampling theory, the quantization of the real values into digital form must also be considered in the performance analysis of a DDS system. The spurious response of a DDS system is primarily dictated by two quantization parameters. These parameters are the phase quantization by the phase accumulator and the magnitude quantization by the ROM sinusoidal table and the DAC.As mentioned above, only the upper Y bits of the phase accumulator are used to address the ROM lookup table. It should be noted, however, that using only the upper Y bits of the phase accumulator introduces a phase truncation. When a frequency word containing a non-zero value in the lower (N-Y-1:0) bits is loaded into the DDS system, the lower non-zero bits will accumulate to the upper Y bits and cause a phase truncation. The frequency at which the phase truncation occurs can be calculated by the following: Ftrunc = FW(N-Y- 1:0)/2N-Y * Fclk. A phase truncation will periodically (at the Ftrunc rate) phase modulate the output carrier forward 2/ to compensate for frequency word granularity greater than . The phase jump caused by the accumulation of phase truncated bits produces spurs around the fundamental.These spurs are located plus and minus the truncation frequency from the fundamental frequency and the magnitude of the spurs will be - 20log()dBc. A sample output of a phase truncation spur is shown in Figure 5.In a typical NCO design, the ROM sinusoidal table will hold a sine wave (0 , /