msp430混合信号微控制器-外文文献及翻译.doc

本科毕业设计
外文文献及译文

文献、资料题目：MPS430 Mixed Signal Microcontroller
文献、资料来源：期刊（著作、网络等）
文献、资料发表（出版）日期：2005.3.25
学 院：信息与电气工程学院
专 业： 通信工程
班 级： 通信
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学 号：
指导教师：
翻译日期：

xx建筑大学毕业设计外文文献及译文
外文文献：　
MSP430 MIXED SIGNAL MICROCONTROLLER
_ Low Supply-Voltage Range, 1.8 V . . . 3.6 V
_ Ultralow-Power Consumption:
− Active Mode: 330μA at 1 MHz, 2.2 V
− Standby Mode: 1.1μA
− Off Mode (RAM Retention): 0.1μA
_ Five Power-Saving Modes
_ Wake-Up From Standby Mode in less than 6μs
_ 16-Bit RISC Architecture, 125-ns Instruction Cycle Time
_ Three-Channel Internal DMA
_ 12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan Feature
_ Dual 12-Bit D/A Converters With Synchronization
_ 16-Bit Timer_A With Three Capture/Compare Registers
_ 16-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers
_ On-Chip Comparator
_ Serial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface
_ Serial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface
_ Supply Voltage Supervisor/Monitor With Programmable Level Detection
_ Brownout Detector
_ Bootstrap Loader
_ Serial Onboard Programming, No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
_ Family Members Include:
− MSP430F155:
16KB+256B Flash Memory
512B RAM
− MSP430F156:
24KB+256B Flash Memory
1KB RAM
− MSP430F157:
32KB+256B Flash Memory,
1KB RAM
− MSP430F167:
32KB+256B Flash Memory,
1KB RAM
− MSP430F168:
48KB+256B Flash Memory,
2KB RAM
− MSP430F169:
60KB+256B Flash Memory,
2KB RAM
− MSP430F1610:
32KB+256B Flash Memory
5KB RAM
− MSP430F1611:
48KB+256B Flash Memory
10KB RAM
− MSP430F1612:
55KB+256B Flash Memory
5KB RAM
_ Available in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN (see Available Options)
_ For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide,
Literature Number SLAU049
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs.
The MSP430x15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous
communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430x161x series offers
extended RAM addressing for memory-intensive applications and large C-stack requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
MSP430F169 MIXED SIGNAL MICROCONTROLLER

short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in
conjunction with seven addressing modes for source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.
instruction set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
_ Active mode AM;
− All clocks are active
_ Low-power mode 0 (LPM0);
− CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
_ Low-power mode 1 (LPM1);
− CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
_ Low-power mode 2 (LPM2);
− CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
_ Low-power mode 3 (LPM3);
− CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
_ Low-power mode 4 (LPM4);
− CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
interrupt enable 1 and 2

WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
OFIE: Oscillator-fault-interrupt enable
NMIIE: Nonmaskable-interrupt enable
ACCVIE: Flash memory access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable

URXIE1 : USART1: UART and SPI receive-interrupt enable
UTXIE1 : USART1: UART and SPI transmit-interrupt enable
URXIE1 and UTXIE1 are not present in MSP430x15x devices.
interrupt flag register 1 and 2

WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag

URXIFG1 : USART1: UART and SPI receive flag
UTXIFG1 : USART1: UART and SPI transmit flag
module enable registers 1 and 2

URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable

URXE1 : USART1: UART mode receive enable
UTXE1 : USART1: UART mode transmit enable
USPIE1 : USART1: SPI mode transmit and receive enable
URXE1, UTXE1, and USPIE1 are not present in MSP430x15x devices.

flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
_ Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
_ Segments 0 to n may be erased in one step, or each segment may be individually erased.
_ Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory.
_ New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.
oscillator and system clock
The clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 ìs. The basic clock module provides the following clock signals:
_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
_ Main clock (MCLK), the system clock used by the CPU.
_ Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
_ All individual I/O bits are independently programmable.
_ Any combination of input, output, and interrupt conditions is possible.
_ Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
_ Read/write access to port-control registers is supported by all instructions.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
hardware multiplier (MSP430x16x/161x Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.
oscillator and system clock
The clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6μs. The basic clock module provides the following clock signals:
_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
_ Main clock (MCLK), the system clock used by the CPU.
_ Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min) If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
_ All individual I/O bits are independently programmable.
_ Any combination of input, output, and interrupt conditions is possible.
_ Edgeselectable interrupt input capability for all the eight bits of ports P1 and P2.
_ Read/write access to port-control registers is supported by all instructions.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
hardware multiplier (MSP430x16x/161x Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
USART0
The MSP430x15x and the MSP430x16x(x) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data