8051系列微控制器--毕业论文外文文献翻译毕业论文.doc

英文资料及中文翻译
Overview
The 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.
The basic architecture consists of the following features:
1· an eight bit ALU
2· 32 descrete I/O pins (4 groups of 8) which can be individually accessed
3· two 16 bit timer/counters
4· full duplex UART
5· 6 interrupt sources with 2 priority levels
6· 128 bytes of on board RAM
7· separate 64K byte address spaces for DATA and CODE memory
One 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).
Memory Organization
The 8051 architecture provides the user with three physically distinct memory spaces which can be seen in Figure A - 1. Each memory space consists of contiguous addresses from 0 to the maximum size, in bytes, of the memory space. Address overlaps are resolved by utilizing instructions which refer specifically to a given address space. The three memory spaces function as described below.
The CODE Space
The first memory space is the CODE segment in which the executable program resides. This segment can be up to 64K (since it is addressed by 16 address lines) . The processor treats this segment as read only and will generate signals appropriate to access a memory device such as an EPROM. However, this does not mean that the CODE segment must be implemented using an EPROM. Many embedded systems these days are using EEPROM which allows the memory to be overwritten either by the 8051 itself or by an external device. This makes upgrades to the product easy to do since new software can be downloaded into the EEPROM rather than having to disassemble it and install a new EPROM. Additionally, battery backed SRAM can be used in place of an EPROM. This method offers the same capability to upload new software to the unit as does an EEPROM, and does not have any sort of read/write cycle limitations such as an EEPROM has. However, when the battery supplying the RAM eventually dies, so does the software in it. Using an SRAM in place of an EPROM in development systems allows for rapid downloading of new code into the target system. When this can be done, it helps avoid the cycle of programming/testing/erasing with EPROM, and can also help avoid hassles over an in circuit emulator which is usually a rare commodity.
In addition to executable code, it is common practice with the 8051 to store fixed lookup tables in the CODE segment. To facilitate this, the 8051 provides instructions which allow rapid access to tables via the data pointer (DPTR) or the program counter with an offset into the table optionally provided by the accumulator. This means that oftentimes, a table's base address can be loaded in DPTR and the element of the table to access can be held in the accumulator. The addition is performed by the 8051 during the execution of the instruction which can save many cycles depending on the situation. An example of this is shown later in this chapter in.
The DATA Space
The second memory space is the 128 bytes of internal RAM on the 8051, or the first 128 bytes of internal RAM on the 8052. This segment is typically referred to as the DATA segment. The RAM locations in this segment are accessed in one or two cycles depending on the instruction. This access time is much quicker than access to the XDATA segment because memory is addressed directly rather than via a memory pointer such as DPTR which must first be initialized. Therefore, frequently used variables and temporary scratch variables are usually assigned to the DATA segment. Such allocation must be done with care, however, due to the limited amount of memory in this segment.
Variables stored in the DATA segment can also be accessed indirectly via R0 or R1. The register being used as the memory pointer must contain the address of the byte to be retrieved or altered. These instructions can take one or two processor cycles depending on the source/destination data byte.
The DATA segment contains two smaller segments of interest. The first sub segment consists of the four sets of register banks which compose the first 32 bytes of RAM. The 8051 can use any of these four groups of eight bytes as its default register bank. The selection of register banks is changeable at any time via the RS1 and the RS0 bits in the Processor Status Word (PSW). These two bits combine into a number from 0 to 3 (with RS1 being the most significant bit) which indicates the register bank to be used. Register bank switching allows not only for quick parameter passing, but also opens the door for simplifying task switching on the 8051.
The second sub-segment in the DATA space is a bit addressable segment in which each bit can be individually accessed. This segment is referred to as the BDATA segment. The bit addressable segment consists of 16 bytes (128 bits) above the four register banks in memory. The 8051 contains several single bit instructions which are often very useful in control applications and aid in replacing external combinatorial logic with software in the 8051 thus reducing parts count on the target system. It should be noted that these 16 bytes can also be accessed on a "byte-wide" basis just like any other byte in the DATA space.
Special Function Registers
Control registers for the interrupt system and the peripherals on the 8051 are contained in internal RAM at locations 80 hex and above. These registers are referred to as special function.
Registers (or SFR for short). Many of them are bit addressable. The bits in the bit addressable SFR can either be accessed by name, index or bit address. Thus, you can refer to the EA bit of the Interrupt Enable SFR as EA, IE.7, or 0AFH. The SFR control things such as the function of the timer/counters, the UART, and the interrupt sources as well as their priorities. These registers are accessed by the same set of instructions as the bytes and bits in the DATA segment. A memory map of the SFRS indicating the registers.
The IDATA Space
Certain 8051 family members such as the 8052 contain an additional 128 bytes of internal RAM which reside at RAM locations 80 hex and above. This segment of RAM is typically referred to as the IDATA segment. Because the IDATA addresses and the SFR addresses overlap, address conflicts between IDATA RAM and the SFRs are resolved by the type of memory access being performed, since the IDATA segment can only be accessed via indirect addressing modes.
The XDATA Space.
The final 8051 memory space is 64K in length and is addressed by the same 16 address lines as the CODE segment. This space is typically referred to as the external data memory space (or the XDATA segment for short). This segment usually consists of some sort of RAM (usually an SRAM) and the I/O devices or external peripherals to which the 8051 must interface via its bus. Read or write operations to this segment take a minimum of two processor cycles and are performed using either DPTR, R0, or R1. In the case of DPTR, it usually takes two processor cycles or more to load the desired address in addition to the two cycles required to perform the read or write operation. Similarly, loading R0 or R1 will take minimum of one cycle in addition to the two cycles imposed by the memory access itself. Therefore, it is easy to see that a typical operation with the XDATA segment will, in general, take a minimum of three processor cycles. Because of this, the DATA segment is a very attractive place to store any frequently.
It is possible to fill this segment entirely with 64K of RAM if the 8051 does not need to perform any I/O with devices in its bus or if the designer wishes to cycle the RAM on and off when I/O devices are being accessed via the bus. Methods for performing this technique will be discussed in chapters later in this book.
On-Board Timer/Counters
The standard 8051 has two timer/counters (other 8051 family members have varying amounts), each of which is a full 16 bits. Each timer/counter can be function as a free running timer (in which case they count processor cycles) or can be used to count falling edges on the signal applied to their respective I/O pin (either T0 or T1). When used as a counter, the input signal must have a frequency equal to or lower than the instruction cycle frequency divided by 2 (ie: the oscillator frequency /24) since the incoming signal is sampled every instruction cycle, and the counter is incremented only when a 1 to 0 transition is detected (which will require two samples). If desired, the timer/counters can force a software interrupt when they overflow.
The TCON (Timer Control) SFR is used to start or stop the timers as well as hold the overflow flags of the timers. The TCON SFR is detailed below in Table A - 7. The timer/counters are started or stopped by changing the timer run bits (TR0 and TR1) in TCON. The software can freeze the operation of either timer as well as restart the timers simply by changing the Trx bit in the TCON register. The TCON register also contains the overflow flags for the timers. When the timers overflow, they set their respective flag (TF0 or TF1) in this register. When the processor detects a 0 to 1 transition in the flag, an interrupt occurs if it is enabled. It should be noted that the software can set or clear this flag at any time. Therefore, an interrupt can be prevented as well as forced by the software.
Microcomputer interface
A microcomputer interface converts information between two forms .Outside the microcomputer the information handled by an electronic system exists as a physical signals, but within the program , it is represented numerically . The function of any interface can be broken down into a number of operations which modify the data in some way ,so than the process of conversion between the external and internal forms is carried out in a number or steps.
This can be illustrated by means of an example such as than or Fig 10-1,which shows an interface between a microcomputer and a transducer producing a continuously variable analog signal. transducers often produce very small out requiring amply frication, or they may generate signals .in a form that needs to be converted again before being handled by the rest of the system .For example ,many transducers these variable resistance which must be converted to a voltage by a special circuit. This process of converting the transducer output into a voltage4 signal which can be connected to the rest of the system is called signal conditioning .In the example of Figure 10-1, the sigma conditioning section translates the range lf voltage or current signals from the transducer to one which can be converted to digital forum by an analog-to-digital converter.

Transducer

A DC

Signal conditioning

I/O
Section

Fig 10-1 output Interface
Analog-to-digital –digital converter (ADC) is used to convert a continuously variable signal to a corresponding digital forum which can take any one of a fixed number of possible binary values .If the output lf the transducer does not vary continuously ,no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section lf the microcomputer itself.
The I/O section converts digital “on/off” voltage signals to a form which can be presented to the processor via the via the system buses .Here the state of each input line whether it is “on” or “off”, is indicated by a corresponding “1” or “0”.In the line inputs which have been converted to digital form, the patterns of ones and zeros in the internal representation will form binary numbers corresponding to the quantity being converted.
The “raw” numbers from the interface are limited by the design of the interface circuitry and they often require linearization and scaling to produce values suitable for use in the main program. For example ,the interface night be rise to convert temperatures in the range –20 to – +50 dress, buy the numbers produced by an 8-bit converter will lie in the range 0 to 255.Obviously it is easier , the programmer‘s point of view to deal directly with temperature rather than to work out the equivalent of any given temperature in terms of the numbers produced by the ADC .Every time the interface is used to read a transducer ,the same operations must be carried out to convert the input number into a more convenient form .Addtionarly ,the operation of some interfaces requires control signals to be passed between the microcomputer and components of the interface ,For these reasons it is normal to use a subroutine to loot after the detailed operation of the interface and carry out any scaling and /or linearization which might be needed.
Output interfaces take a similar form (Fig.10-2), the biopic difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for a digital-to-analog converter (DAC) .This subroutine passes information in term to an out analog form using a DAC .Finally the signal is conditioned (usually amplified ) to a form suitable for operating an actuator.

Fig 10-2 output Interface

The signals used within mi