ds1302涓流充电时钟芯片--外文文献翻译.doc

DS1302涓流充电时钟芯片
一、特性
1、实时时钟，可对秒、分、时、日、周、月以及带闰年补偿的年进行计数,有效期2100年；
2、用于高速数据暂存的31×8 RAM；
3、最少引脚数的串行I/O；
4、2.0-5.5V满度工作范围；
5、2.5V时耗电小于300nA；
6、用于时钟或RAM数据读/写的单字节或多字节（脉冲方式）数据传送；
7、8引脚DIP或可选的用于表面安装的8引脚SOIC封装；
8、简单的3线接口；
9、TTL兼容（VCC=5V）；
10、可选的工业温度范围-40℃至+85℃；
11、与DS1202兼容。
二、引脚排列
DS1302引脚封装图如下图1所示

图1 DS1302引脚封装图
三、引脚说明
①X1，X2：32.768kHz晶振引脚；②GND：接地；③RST：复位；④I/O：数据输入/输出；⑤SCLK：串行时钟；⑥VCC1，VCC2：电源引脚。
四、说明
DS1302慢速充电时钟芯片包括实时时钟/日历和31字节的静态RAM。它经过一个简单的串行接口与微处理器通信。实时时钟/日历提供秒、分、时、日、周、月和年等信息。对于小于31天的月，月末的日期自动进行调整，还包括了闰年校正的功能。时钟的运行可以采用24小时或带AM（上午）/PM（下午）的12小时格式。使用同步串行通信，简化了DS1302与微处理器的通信。与时钟/RAM通信仅需三根线：（1）RST（复位）、（2）I/O（数据线）、和（3）SCLK（串行时钟）。数据可以以每次一个字节或多达31字节的多字节形式传送至时钟/RAM或从其中送出。DS1302设计成能在非常低的功耗下工作，消耗小于1微瓦的功率便能保存数据和时钟信息。
DS1302是DS1202的升级产品，除了DS1202基本的慢速充电功能外，DS1302具有的其它特点包括：用于主电源和备份电源的双电源引脚，可编程的VCC1慢速充电器以及7个附加字节的高速暂存存储器（scratchpad memory）。
（1）工作原理
串行时钟芯片的主要组成部分示于图2：移位寄存器、控制逻辑、振荡器、实时时钟以及RAM。

图2 DS1302方框图
（2）信号说明
①VCC1：VCC1在单电源与电池供电的系统中提供低电源并提供低功率的电池备份。通过连接这个引脚对系统实时充电；
②VCC2：VCC2在双电源系统中提供主电源，在这种运用方式中VCC1连接到备份电源，以便在没有主电源的情况下能保存时间信息以及数据；
③DS1302由VCC1或VCC2两者中较大者供电。当VCC2大于VCC1+0.2V时，VCC2给DS1302供电。当VCC2小于VCC1时，DS1302由VCC1供电；
④时钟（串行时钟输入） -时钟用于同步数据移动的串行接口；
⑤I/O（数据输入/输出）-对I/O引脚是双向数据引脚的3线接口；
⑥复位（复位） -复位信号必须在高电平读取或写入；
⑦X1，X2：连接为一个标准的32.768 kHz的石英晶体。所选用晶振规定的负载电容量应当为6pF。
（3）命令字节
命令字节示于图3。每一数据传送由命令字节初始化。最高有效位MSB（位7）必须为逻辑1。如果它是零，禁止写DS1302。位6为逻辑0指定时钟/日历数据；逻辑1指定RAM数据。位1至5指定进行输入或输出的特定寄存器。最低有效位LSB（位0）为逻辑0指定进行写操作（输入）；逻辑1指定进行读操作（输出）。命令字节总是从最低有效LSB（位0）开始输入。

图3 地址/命令字节
（4）复位和时钟控制
通过把RST输入驱动至高电平来启动所有的数据传送。RST输入有两种功能。首先，RST接通控制逻辑，允许地址/命令序列送入移位寄存器。其次，RST提供了中止单字节或多字节数据传送的手段。时钟是下降沿后继以上升沿的序列。数据输入时，在时钟的上升沿数据必须有效，而数据位在时钟的下降沿输出。如果RST输入为低电平，那么所有的数据传送中止且I/O引脚变为高阻抗状态。数据传送在图4中说明。上电时，在VCC≥2.0伏之前RST必须为逻辑0。此外，当把RST驱动至逻辑1的状态时，SCLK必须为逻辑0。

图4数据传输概要
（5）数据输入
跟随在输入写命令字节的8个SCLK周期之后，在下8个SCLK周期的上升沿输入数据字节。如果有额外的SCLK周期，它们将被忽略。数据从位0开始输入。
（6）数据输出
跟随在输入读命令字节的8个SCLK周期之后，在下8个SCLK周期的下降沿输出数据字节。注意，被传送的第一个数据位发生在写命令字节的最后一位之后的第一个下降沿。只要RST保持为高电平，如果有额外的SCLK周期，它们将重新发送数据字节。这一操作使之具有连续的多字节方式的读能力。另外，在SCLK的每一上升沿，I/O引脚为三态。数据从位0开始输出。
（7）多字节方式
通过对地址31（十进制）寻址（地址/命令位1至5=逻辑1），可以把时钟/日历或RAM寄存器规定为多字节（burst）方式。如前所述，位6规定时钟或RAM而位0规定读或写。在时钟/日历寄存器中的地址9至31或RAM寄存器中的地址31不能存储数据。在多字节方式中读或写从地址0的位0开始。与使用DS1202时一样，当以多字节方式写时钟寄存器时，必须按数据传送的次序写最先8个寄存器。但是，当以多字节方式写RAM时，为了传送数据不必写所有31个字节。不管是否写了全部31个字节，所写的每一个字节都将传送至RAM。
（8）时钟/日历
如图5所示，时钟/日历包含在7个写/读寄存器内。包含在时钟/日历寄存器内的数据是二——十进制（BCD）码。

图5 DS1320寄存器说明
（9）时钟暂停
秒寄存器的位7定义为时钟暂停位。当此位设置为逻辑1时，时钟振荡器停止，DS1302被置入低功率的备份方式，其电源消耗小于100毫微安（nanoamp）。当把此位写成逻辑0时，时钟将启动。
（10）AM-PM/12-24方式
小时寄存器的位7定义为12或24小时方式选择位。当它为高电平时，选择12小时方式。在12小时方式下，位5是AM/PM位，此位为逻辑高电平表示PM。在24小时方式下，位5是第2个10小时位（20-23时）。
（11）写保护寄存器
写保护寄存器的位7是写保护位。开始7位（位0-6）置为零，在读操作时总是读出零。在对时钟或RAM进行写操作之前，位7必须为零。当它为高电平时，写保护位防止对任何其它寄存器进行写操作。
（12）慢速充电（Trickle charge）寄存器
这个寄存器控制DS1302的慢速充电特性。图5的简化电路表示慢速充电器的基本组成。慢速充电选择（TCS）位（位4-7）控制慢速充电器的选择。为了防止偶然的因素使之工作，只有1010模式才能使慢速充电器工作，所有其它的模式将禁止慢速充电器。DS1302上电时，慢速充电器被禁止。二极管选择（DS）位（位2-3）选择是一个二极管还是两个二极管连接在VCC2与VCC1之间。如果DS为01，那么选择一个二极管；如果DS为10，则选择两个二极管。如果DS为00或11，那么充电器被禁止，与TCS无关。RS位（位0-1）选择连接在VCC2与VCC1之间的电阻。电阻选择（RS）位选择的电阻如下表1：
表1 电阻选择（RS）位选择的电阻

如果RS为00，充电器被禁止，与TCS无关。
二极管和电阻的选择由用户根据电池或超容量电容充电所需的最大电流决定。最大充电电流可以如下列所说明的那样进行计算。假定5V系统电源加到VCC2而超容量电容接至VCC1。再假设慢速充电器工作时在VCC2和VCC1之间接有一个二极管和电阻R1。因而最大电流可计算如下：

Imax=（5.0V－二极管压降）/R1
～（5.0V－0.7V）/2kΩ
～2.2mA
显而易见，当超容量电容充电时，VCC2和VCC1之间的电压减少，因而充电电流将会减小。
（13）时钟/日历多字节（Burst）方式
时钟/日历命令字节可规定多字节工作方式。在此方式下，最先8个时钟/日历寄存器可以从地址0的第0位开始连续地读或写（见图5）。当指定写时钟/日历的多字节方式时，如果写保护位设置为高电平，那么没有数据会传送到8个时钟/日历寄存器（包括控制寄存器）的任一个。在多字节方式下，慢速充电器是不可访问的。
（14）RAM
静态RAM是RAM地址空间中顺序寻址的31×8字节。
（15）RAM多字节方式
RAM命令字节可规定多字节工作方式。在此方式下，可以从地址0的第0位开始顺序读或写31 RAM寄存器（见图5）。
（16）寄存器概要
寄存器数据格式概要示于图5。
（17）晶振选择
32.768kHz的晶振（诸如Daiwa公司的DT26S、Seiko公司的DS-VT-200或其他类似产品）可通过引脚2和3（X1，X2）直接连接至DS1302。所选用晶振规定的负载电容量（CL）应当为6pF。晶振可从Dallas半导体公司订购。订购器件号是DS9032。
五、极限参数*
任何引脚相对于地的电压 –0.5V至+7.0V
运用温度 0℃至70℃
贮存温度 –55℃至+125℃
焊接温度 260℃，10秒
* 强度超出所列的极限参数可能导致器件的永久性损坏。这些仅仅是极限参数，并不意味着在极限条件下或在任何其它超出推荐工作条件所示参数的情况下器件能有效地工作。延长在极限参数条件下的工作时间会影响器件的可靠性。
六、推荐的直流运用条件
推荐的直流运用条件见下表2
表2 直流运用条件表

七、直流电特性
直流特性见下表3
表3 直流特表

八、电容
电容见下表 4
表4 电容说明表

九、交流电特性
交流特性见下表5
表5 交流特性说明表

十、时序图
读数据传输时序图见下图6

图6 读数据传输
写数据传输时序图见下图7

图7 写数据传输
十一、注意
1. 所有电压以地为参考点。
2. 对于电容性负载,提供电流1mAVCC=5V和0.4mA、VCC=2.5V、VOH=VCC条件下规定逻辑1的电压。
3. 对于电容性负载，在吸收电流4mA、VCC=5V和1.5mA、VCC=2.5V、VOL=地的条件下规定逻辑0的电压。
4. 在I/O开路、RST设置为逻辑0、时钟暂停标志=0（允许振荡器工作）条件下规定ICC1T和ICC2T。
5. 在I/O引脚开路、RST设置为高电平、VCC=5V时SCLK=2MHz；VCC=2.5V时SCLK= 500kHz以及时钟暂停标志=0（允许振荡器工作）的条件下规定ICC1A和ICC2A。
6. RST、SCLK和I/O均接有40kΩ下拉电阻至地。
7. 在VIH=2.0V或VIL=0.8V以及最大为10ms上升和下降时间条件下测量。
8. 在VOH=2.4V或VOL=0.4V条件下测量。
9. 负载电容=50pF。
10. 在RST、I/O和SCLK开路条件下规定ICC1S和ICC2S。时钟暂停标志必须设置为逻辑1（禁止振荡器工作）。
11. 当VCC2>VCC1+0.2V时，VCC=VCC2；当VCC1>VCC2时，VCC=VCC1。
12. VCC2=0伏。
13. VCC1=0伏。
14. 典型值为25℃时的数值。

附录B 外文原文

DS1302 Trickle Charge Timekeeping Chip
一、FEATURES
1、Real time clock counts seconds, minutes hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100.
2、31 x 8 RAM for scratchpad data storage.
3、Serial I/O for minimum pin count.
4、2.0–5.5V full operation.
5、Uses less than 300 nA at 2.0V.
6、Single–byte or multiple–byte (burst mode) data transfer for read or write of clock or RAM data.
7、8–pin DIP or optional 8–pin SOICs for surface mount.
8、Simple 3–wire interface.
9、TTL–compatible (VCC = 5V).
10、Optional industrial temperature range –40°C to +85°C.
11、DS1202 compatible
二、PIN ASSIGNMENT

三、PIN DESCRIPTION
①X1, X2：32.768 kHz Crystal Pins；②GND：Ground；③RST：Reset；④I/O：Data Input/Output；⑤SCLK：Serial Clock；⑥VCC1, VCC2：Power Supply Pins
四、DESCRIPTION
The DS1302 Trickle Charge Timekeeping Chip contains a real time clock/calendar and 31 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. The clock operates in either the 24–hour or 12–hour format with an AM/PM indicator. Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: (1) RST(Reset), (2) I/O (Data line), and (3) SCLK (Serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1 microwatt.
The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the DS1302 has the additional features of dual power pins for primary and back–up power supplies, programmable trickle charger for VCC1, and seven additional bytes of scratchpad memory.
（1）OPERATION
The main elements of the Serial Timekeeper are shown in Figure 1: shift register, control logic, oscillator,real time clock, and RAM.

DS1302 BLOCK DIAGRAM Figure 1

（2）SIGNAL DESCRIPTIONS
①VCC1： VCC1 provides low power operation in single supply and battery operated systems as well as low power battery backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin.
②VCC2 ：Vcc2 is the primary power supply pin in a dual supply configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power.
③The DS1302 will operate from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 will power the DS1302. When VCC2 is less than VCC1, VCC1 will power the DS1302.
④SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface.
⑤I/O (Data Input/Output) – The I/O pin is the bi-directional data pin for the 3-wire interface.

⑥RST (Reset) – The reset signal must be asserted high during a read or a write.
⑦X1, X2 ： Connections for a standard 32.768 kHz quartz crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6 pF.
（3）COMMAND BYTE
The command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
ADDRESS/COMMAND BYTE Figure 2

（4）RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input high. The RST input serves two functions. First, RST turns on the control logic which allows access to the shift register for the address/command sequence. Second, the RST signal provides a method of terminating either single byte or multiple byte data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the I/O pin goes to a high impedance state. Data transfer is illustrated in Figure 3. At power–up, RST must be a logic 0 until VCC > 2.0 volts. Also SCLK must be at a logic 0 when RST is driven to a logic 1 state.
DATA TRANSFER SUMMARY Figure 3

（5）DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0.
（6）DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as RST remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri–stated upon each rising edge of SCLK. Data is output starting with bit 0.
（7）BURST MODE
Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not.
（8）CLOCK/CALENDAR
The clock/calendar is contained in seven write/read registers as shown in Figure 4. Data contained in the clock/ calendar registers is in binary coded decimal format (BCD).
REGISTER ADDRESS/DEFINITION Figure 4：

（9）CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low–power standby mode with a current drain of less than 100 nanoamps. When this bit is written to logic 0, the clock will start. The initial power on state is not defined.
（10）AM-PM/12-24 MODE
Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10-hour bit (20 – 23 hours).
（11）WRITE PROTECT BIT
Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 – 6) are forced to 0 and will always read a 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write protect bit prevents a write operation to any other register. The initial power on state is not defined. Therefore the WP bit should be cleared before attempting to write to the device.
（12）TRICKLE CHARGE REGISTER
This register controls the trickle charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits 4 -7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010 will enable the trickle charger. All other patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2 – 3) select whether one diode or two diodes are connected between VCC2 and VCC1. If DS is 01, one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0 -1) select the resistor that is connected between VCC2 and VCC1. The resistor selected by the resistor select (RS) bits is as follows.

If RS is 00, the trickle charger is disabled independently of TCS.
Diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 5 volt is applied to VCC2 and a super cap is connected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum current Imax would therefore be calculated as follows:
Imax = (5.0V – diode drop) / R1
~ (5.0V – 0.7V) / 2 kΩ
~ 2.2 Ma
Obviously, as the super cap charges, the voltage drop between VCC2 and VCC1 will decrease and thereforethe charge current will decrease.
（13）CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst mode operation. In this mode the first eight clock/calendar registers can be consecutively read or written (see Figure 4) starting with bit 0 of address 0. If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode. At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
（14）RAM
The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.
（15）RAM BURST MODE
The RAM command byte specifies