EDA-常见实例源程序代码vhdl.doc

第4章 用VHDL程序实现常用逻辑电路
4.1 组合逻辑电路设计
4.1.1 基本逻辑门
library ieee;
use iee.std_logic_1164.all;
entity jbm is
port(a,b: in bit;
f1,f2,f3,f4,f5,f: out bit);
end jbm;
architecture a of jbm is
begin
f1<=a and b; --构成与门
f2<=a or b; --构成或门
f<=not a; --构成非门
f3<=a nand b; --构成与非门
f4<=a nor b; --构成异或门
f5<=not(a xor b); --构成异或非门即同门
end;
4.1.2 三态门
library ieee;
use ieee.std_logic_1164.all;
entity tri_s is
port(enable: in std_logic;
datain: in std_logic_vector(7 downto 0);
dataout: out std_logic_vector(7 downto0));
end tri_s;
architecture bhv of tri_s is
begin
process(enable,datain)
begin
if enable='1' then
dataout<=datain;
else
dataout<="ZZZZZZZZ";
end if;
end process;
end bhv;
4.1.3 3-8译码器
library ieee;
use ieee.std_logic_1164.all;
entity decoder3_8 is
port(a,b,c,g1,g2a,g2b: in std_logic;
y: out std_logic_vector(7 downto 0));
end decoder3_8;
architecture a of decoder3_8 is
signal dz:std_logic_vector(2 downto 0);
begin
dz<=c&b&a;
process (dz,g1,g2a,g2b)
begin
if(g1='1'and g2a='0'and g2b='0')then
case dz is
when "111"=> y<="01111111";
when others=>y<="XXXXXXXX";
end case;
else
end if;
end process;
4.1.4 优先编码器
library ieee;
use ieee.std_logic_1164.all
entity coder is
port(din: in std_logic_vector(0 to 7);
output: out std_logic_vector(0 to 2));
end coder;
architecture behave of coder is
signal sint: std_logic_vevtor(4 downto 0);
begin
process(din)
begin
if (din(7)='0') then
output <= "000" ;
elsif (din(6)='0') then
output <= "100" ;
elsif (din(5)='0') then
output <= "010" ;
elsif (din(4)='0') then

output <= "110" ;
elsif (din(3)='0') then
output <= "001" ;
elsif (din(2)='0') then
output <= "101" ;
elsif (din(1)='0') then
output <= "011" ;
else
output <= "111" ;
end if;
end process;
end behav;
4.1.5 7段码译码器
library ieee;
use ieee.std_logic_1164.all
entity decl7s is
port (a: in std_logic_vector (3 downto 0);
led7s: out std_logic_vector(6 downto 0));
end decl7s;
architecture behave of decl7s is
begin
process(a)
begin
case a is
when "0000" => led7s <= "0111111" ;
when "0001" => led7s <= "0000110" ;
when "0010" => led7s <= "1011011" ;
when "0011" => led7s <= "1001111" ;
when "0100" => led7s <= "1100110" ;
when "0101" => led7s <= "1101101" ;
when "0110" => led7s <= "1111101" ;
when "0111" => led7s <= "0000111" ;
when "1000" => led7s <= "1111111" ;
when "1001" => led7s <= "1101111" ;
when "1010" => led7s <= "1110111" ;
when "1011" => led7s <= "1111100" ;
when "1100" => led7s <= "0111001" ;
when "1101" => led7s <= "1011110" ;
when "1110" => led7s <= "1111001" ;
when "1111" => led7s <= "1110001" ;
when others => null;
end case;
end process;
end behave;
4.1.6二-十进制BCD译码器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity bcdymq is
port(din : in integer range 15 downto 0;
a,b : out integer range 9 downto 0);
end;
architecture fpq1 of bcdymq is
begin
p1: process(din)
begin
if din<10 then
a< =din;
b< =0;
else
a< =din-10;
b< =1;
end if;
end process p1;
end;
4.1.7 多位加（减）法器
library ieee;
use ieee.std_logic1164.all;
use ieee.std_logic_signed.all;
entity jianfaqi is
port(a,b : in std_logic_vector(0 to 3);
c0: in std_logic;
c1: out std_logic;
d : out std_logic_vector(0 to 3));
end;
architecture a of jianfaqi is
begin
process
begin
if a>b+c0 then
d<=a-(b+c0);
c1<='0';
else
c1<='1';
d<=("10000")-(b+c0-a);
end if;
end process ;
end ;
4.2 时序逻辑电路设计
4.2.1 触发器
RS触发器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity rsff is
port(r,s,clk:in std_logic;
q,qb:buffer std_logic);
end rsff;
architecture rsff_art of rsff is
signal q_s,qb_s:std_logic;
begin
process(clk,r,s)
begin
if (clk'event and clk='1') then
if (s='1' and r='0') then
q_s<='0' ;
qb_s<='1' ;
elsif (s='0' and r='1') then
q_s <= '1' ;
qb_s <= '0' ;
elsif (s='0' and r='0') then
q_s <= q_s;
qb_s <= qb_s;
end if;
end if;
q_s <= q_s;
qb_s <= qb_s;
end process;
end rsff_art;
同步复位D触发器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity syndff is
port(d,clk,reset:in std_logic;
q,qb:out std_logic);
end syndff;
architecture dff_art of syndff is
begin
process(clk)
begin
if (clk'event and clk='1') then
if (reset='0') then
q<='0';
qb<='1';
else
q<=d;
qb<=not q;
end if;
end if;
end process;
end dff_art;
JK触发器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity asynjkff is
port(j,k,clk,set.reset:in std_logic;
q,qb:out std_logic);
end asynjkff;
architecture jkff_art of asynjkff is
singal q_s,qb_s:std_logic;
begin
process(clk,set,reset)
begin
if (set='0' and reset='1' ) then
q_s<='1';
qb_s<='0';
elsif (set='1' and reset='0' ) then
q_s<='0';
qb_s<='1';
elsif (clk'event and clk='1') then
if (j='0' and k='1' ) then
q_s<='0';
qb_s<='1';
elsif (j='1' and k='0' ) then
q_s<='1';
qb_s<='0';
elsif (j='1' and k='1' ) then
q_s<=not q_s;
qb_s<=not qb_s;
end if;
end if;
q<= q_s;
qb<= qb_s;
end process;
end jkff_art;
T触发器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity tff is
port(t,clk: in std_logic;
q: out std_logic);
end;
architecture tff_art of tff is
signal q_temp: std_logic;
begin
p1:process(clk)
begin
if rising_edge(clk) then
if t='1' then --当T=1时T触发器具有2分频的功能
q_temp<=not q_temp;
else
q_temp<=q_temp;
end if;
end if;
q<=q_temp;
end process;
q<=q_temp;
end tff_art;
4.2.2计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt4 IS
port( clk: in std_logic;
q: out std_logic_vector(3 downto 0));
end cnt4;
architecture behave of cnt4 is
signal q1: std_logic_vector(3 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
q1<=q1+1;
end if;
end process;
q<=q1;
end behave;
一般计数器设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port( clk,rst,en,updown: in std_logic;
cq: out std_logic_vector(3 downto 0));
end cnt10;
architecture behave of cnt10 is
begin
process(clk,rst,en,updown)
variable cqi:std_logic_vector(3 downto 0);
begin
if rst='1' then
cqi:=(others=>'0'); --计数器异步复位
elsif (clk'event and clk = '1') then --检测时钟上升沿
if en='1'then --检测是否允许计数（同步使能）
if updown='0'then
if cqi<9 then
cqi:=cqi+1; --允许计数,检测是否小于9
else
cqi:=(others=>'0'); --大于9，计数值清零
end if;
else
if cqi>0 then
cqi:=cqi-1; --检测是否大于0
else
cqi:=(others=>'1'); ---否则，计数值置1
end if;
end if
end if;
end if;
cq<=cqi; --将计数值向端口输出
end process;
end behave;
4.2.3 分频器
library ieee;
use std_logic_1164.all;
use std_logic_unsigned.all;
entity freq1 is
port(clk: in std_logic;
d: in std_logic_vector(7 downto 0);
fout: out std_logic);
end;
architecture one of dvf is
signal full: std_logic;
begin
p_reg:process(clk)
variable cnt8: std_logic_vector(7 downto 0);
begin
if clk'event and clk='1'then --检测时钟上升沿
if cnt8='''' then
cnt8:=d; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8

full<='1'; --同时使溢出标志信号FULL输出为高电平
else
cnt8:=cnt8+1; --否则继续作加1计数
full<='0'; --且输出溢出标志信号FULL为低电平
end if;
end if;
end process p_reg;
p_div:process(full)
variable cnt2: std_logic;
begin
if full'event and full='1' then
cnt2:=not cnt2; --如果溢出标志信号FULL为高电平，T触发器输出取反
if cnt2='1'then
fout<='1';
else
fout<='0';
end if;
end if;
end process p_div;
end;
4.2.4 移位寄存器
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(clk,c0: in std_logic; --时钟和进位输入
md: in std_logic_vector(2 downto 0); --移位模式控制字
d: in std_logic_vector(7 downto 0); --待加载移位的数据
qb: out std_logic_vector(7 downto 0); --移位数据输出
cn: out std_logic); --进位输出
end;
architecture behave of shift is
signal reg: std_logic_vector(7 downto 0);
signal cy: std_logic;
begin
process(clk,md,c0)
begin
if clk'event and clk='1' then
case md is
when "001" => reg (0) <= c0 ;
reg (7 downto 1) <= reg (6 downto 0);
cy <= reg (7); --带进位循环左移
when "010" => reg (0) <= reg (7);
reg (7 downto 1) <= reg (6 downto 0); --自循环左移
when "011" => reg (7) <= reg (0);
reg (6 downto 0) <= reg (7 downto 1); --自循环右移
when "100" => reg (7) <= C0 ;
reg (6 downto 0) <= reg (7 downto 1);
cy <= reg (0); --带进位循环右移
when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数
when others => reg<= reg ; cy<= cy ; --保持
end case;
end if;
end process;
qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出
end behav;
4.3 状态机逻辑电路设计
4.3.1 一般状态机设计
library ieee;
use ieee.std_logic_1164.all;
entity s_machine is
port ( clk,reset : in std_logic;
state_inputs : in std_logic_vector(0 to1);
comb_outputs : out integer range 0 to 15 );
end s_machine;
architecture behv of s_machine is
type fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化
signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型
begin
reg: process(reset,clk) --主控时序进程
begin
if reset = '1' then
current_state <= s0; --检测异步复位信号
elsif clk='1' and clk'event then
current_state <= next_state;
end if;
end process;
com:process(current_state, state_inputs) --主控组合进程
begin
case current_state is
when s0 => comb_outputs<= 5;
if state_inputs = "00" then
next_state<=s0;
else
next_state<=s1;
end if;
when s1 => comb_outputs<= 8;
if state_inputs = "00" then
next_state<=s1;
else
next_state<=s2;
end if;
when s2 => comb_outputs<= 12;
if state_inputs = "11" then
next_state <= s0;
else
next_state <= s3;

end if;
when s3 => comb_outputs <= 14;
if state_inputs = "11" then
next_state <= s3;
else
next_state <= s0;
end if;
end case;
end process;
end behv;
4.3.2状态机的应用
library ieee;
use ieee.std_logic_1164.all;
entity asm_led is
port(clk,clr : in std_logic;
led1,led2,led3:out std_logic);
end;
architecture a of asm_led is
type states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明
signal q: std_logic_vector( 0 to 2);
signal state : states;
begin
p1: process(clk,clr)
begin

if(clr='0')then
state<=s0;
elsif (clk'event and clk='1') then
case state is
when s0=> state <=s1;
when s1=> state <=s2;
when s2=> state <=s3;
when s3=> state <=s4;
when s4=> state <=s5;
when s5=> state <=s0;
when others => state<=s0;
end case;
end if;
end process p1;
p2: process (clr,state)
begin
if(clr='0') then
led1<='0';
led2<='0';
led3<'0';
else
case state is
when s0=> led1<='1';led2<='0';led3<='0';
when s1=> led1<='0';led2<='1';led3<='0';
when s2=> led1<='0';led2<='1';led3<='0';
when s3=> led1<='0';led2<='0';led3<='1';
when s4=> led1<='0';led2<='0';led3<='1';
when s5=> led1<='0';led2<='0';led3<='1';
when others => null;
end case;
end if;
end process p2;
end ;
第6章 EDA仿真技术应用实例
6.1带使能和片选端的16：4线优先编码器设计
子模块设计源代码：
library ieee;
use ieee.std_logic_1164.all;
entity pencoder is
port(d:in std_logic_vector(7 downto 0);
ei:in std_logic; --ei:enable input
gs,eo:out bit; --gs:chip select output;eo:enable output
q2,q1,q0:out std_logic);
end pencoder;
architecture encoder of pencoder is
begin
process(d)
begin
if(d(0)='0' and ei='0')then
q2<='1';q1<='1';q0<='1';
gs<='0';eo<='1';
elsif(d(1)='0' and ei='0')then
q2<='1';q1<='1';q0<='0';
gs<='0';eo<='1';
elsif(d(2)='0' and ei='0')then
q2<='1';q1<='0';q0<='1';
gs<='0';eo<='1';
elsif(d(3)='0' and ei='0')then
q2<='1';q1<='0';q0<='0';
gs<='0';eo<='1';
elsif(d(4)='0' and ei='0')then
q2<='0';q1<='1';q0<='1';
gs<='0';eo<='1';
elsif(d(5)='0' and ei='0')then
q2<='0';q1<='1';q0<='0';
gs<='0';eo<='1';
elsif(d(6)='0' and ei='0')then
q2<='0';q1<='0';q0<='1';
gs<='0';eo<='1';
elsif(d(7)='0' and ei='0')then --d7 prioty encoder
q2<='0';q1<='0';q0<='0';
gs<='0';eo<='1';
elsif(ei='1')then
q2<='1';q1<='0';q0<='1';
gs<='1';eo<='1';
'0')then
q2<='1';q1<='1';q0<='1';
gs<='1';eo<='0';