数字电路8.3.ppt

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,8.5,shift register,（移位寄存器,）,serial input,Serial-in,S,erial-out,s,tructure,Can be used to delay a signal by,n,clock ticks.,serial output,Serial-in,P,arallel-out,s,tructure,1,Q,2,Q,NQ,parallel-out,Can be used to perform,serial-to-parallel,conversion,serial-in,8.5,shift register,（移位寄存器,）,P,arallel-in,Serial-out,s,tructure,LOAD/SHIFT=1,载入数据,LOAD/SHIFT,SERIN,SEROUT,二选一,LOAD/SHIFT=0,移位,Can be used to perform,parallel-to-serial,conversion,LOAD/SHIFT,SERIN,1,Q,2,Q,NQ,P,arallel-in,P,arallel-out,s,tructure,MSI,Shift Registers,CLK,CLR,SERA,SERB,74,x164,QA,QB,QC,QD,QE,QF,QG,QH,CLK,CLKINH,SH/LD,CLR,SER,A,B,C,D,E,F,G,H,QH,74,x166,74x164:8-bit serial-in,parallel-out shift register,74x166:8-bit parallel-in,serial-out shift register,SERASERB,clock,inhibit,CLK,CLR,S1,S0,LIN,D,QD,C QC,B QB,A QA,RIN,74,x194,left-in,right-in,74x194:4-bit universal shift register(bidirectional),MSI,Shift Registers,S1 S0,S1 S0,10,左移,01,右移,11,载入,Fig.,8-,41,Q,i,*=D,i,=S1S0Q,i,+S1S0Q,i-1,+S1S0Q,i+1,+S1S0IN,i,每个,D,触发器的输入均为一个,“,四选一,”,电路的输出：,00,保持,QD,QC,QB,C,interior,logic of,74x194,CLK,CLR,S1,S0,LIN,D,QD,C QC,B QB,A QA,RIN,74,x194,CLK,CLR,S1,S0,LIN,D,QD,C QC,B QB,A QA,RIN,CLK,CLR,S1,S0,LIN,RIN,移,位,寄,存,器,的,扩,展,并行输入,（8位）,并行,输出,8位,Shift-Register Counters,D,0,=F(Q,0,Q,1,Q,n-1,),Feedback Logic,D Q,CK Q,D Q,CK Q,D Q,CK Q,D Q,CK Q,CLK,计数顺序特殊：既不是升序，也不是降序；,多用于控制领域；,一般结构：,移位寄存器,+,反馈逻辑,(,组合电路,),D,0,Q,0,Q,1,Q,2,Q,3,（移位寄存器计数器）,1000,0100,0001,0010,有效状态,其他状态,Ring Counters,（环型计数器）,D Q,CK Q,D Q,CK Q,D Q,CK Q,D Q,CK Q,CLK,1000,0100,0001,0010,Q0 Q1 Q2 Q3,非自校正的,D,0,=Q,n-1,无效状态,1000,0100,0001,0010,有效状态,其他状态,D Q,CK Q,D Q,CK Q,D Q,CK Q,D Q,CK Q,CLK,1000,0100,0001,0010,Q0 Q1 Q2 Q3,无效状态,self-correcting,自校正的,思考：将“或非门”换成“与非门”如何？,顺序脉冲发生器,Q0,Q1,Q2,Q3,1,0,CLOCK,Q0,Q1,Q2,Q3,1,0,1,0,0,0,Q0,Q1,Q2,Q3,RESET载入,Q0,Q1,Q2,Q3,CLOCK,self-correcting,Ring Counter using 74x194,Johnson Counter,（,扭环计数器,）,D Q,CK Q,D Q,CK Q,D Q,CK Q,D Q,CK Q,CLK,D,0,=Q,n-1,0000,1000,1100,1110,1111,0111,0011,0001,无效,有效的状态循环,如何得到自校正的扭环计数器？,twisted-ring counter,self-correcting design,当状态机进入无效状态时，改变其状态转移方向，迫使其回到有效状态循环中。,Q0Q1Q2Q3,：,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,Q0Q1,00,01,11,10,00,01,11,10,Q2Q3,D0,1,0000,1000,1100,1110,1111,0111,0011,0001,有,效,无,效,1001,0100,1010,1101,0110,1011,0101,0010,1,D0=Q3+Q2Q0,=(Q3(Q2Q0),=(Q3(Q2Q0),D Q,CK Q,D Q,CK Q,D Q,CK Q,D Q,CK Q,CLK,D0=Q3+Q2Q0,self-correcting design,CLK,CLR,S1,S0,LIN,D,QD,C QC,B QB,A QA,RIN,74,x194,+5,V,CLOCK,RESET_L,S1S0,接成左移形式,self-correcting design,(method 1):,D0=(Q3(Q2Q0),Q0,Q1,Q2,Q3,Johnson Counter using 74x194,CLK,CLR,S1,S0,LIN,D,QD,C QC,B QB,A QA,RIN,74,x194,CLOCK,self-correcting design,(method 2):,利用置数功能,每当电路出现,“0 xx0”,下一状态就是,“1000”,Q0,Q1,Q2,Q3,+5,V,(Q0Q1Q2Q3),Johnson Counter using 74x194,小结：,n,位移位寄存器能够构成模,n,的环形计数器,n,位移位寄存器能够构成模,2n,的扭环形计数器,问题：,实现一个十进制计数器,最少需要,个触发器？,若用环形计数器形式，需要,位移位寄存器？,扭环计数器呢？,线性反馈移位寄存器（,LFSR）,计数器,2,n,-1,states,Maximum-length sequence generator,Structure:,RESET_L,CLOCK,odd-parity circuit,The next state for the all-,0,s state?,Feedback equations:Table 8-21,部分输出位相“异或”，反馈到串行输入端。,Linear Feedback Shift-Register Counters,for n=3,X3=X1,X0,X2 X1 X0,X3=X1,X0,0 0 1,1 0 0,0 1 0,1 0 1,1 1 0,1 1 1,0 1 1,Typical application:,generate pseudorandom sequence.,产生伪随机序列,LFSR,counter can be modified to have,2,n,states.,Fig.8-52,Table 8-27,线性反馈移位寄存器（,LFSR）,计数器,Linear Feedback Shift-Register Counters,2,n,-1,states,Maximum-length sequence generator,Serial/Parallel Conversion,（并/串转换）,源模块,Source module,目的模块,Destination module,控制,电路,控制,电路,并-串,转换器,串-并,转换器,并行,数据,并行,数据,串行数据,SYNC,同步脉冲,并,/,串转换,CLK,CLKINH,SH/LD,CLR,SER,A,B,C,D,E,F,G,H,QH,74,x166,D7,D6,D5,D4,D3,D2,D1,D0,并行数据,SDATA,CLOCK,CLOCK,SYNC,CLK,CLR,LD,ENP,ENT,A QA,B QB,C QC,D QD,RCO,163,CLK,CLR,LD,ENP,ENT,A QA,B QB,C QC,D QD,RCO,163,计,数,低,位,计,数,高,位,时,隙,数,位,数,RESET_L,到,目,标,+5,V,CLK,CLR,SERA,SERB,74,x164,QA,QB,QC,QD,QE,QF,QG,QH,SDATA,CLOCK,CLK,CLR,LD,ENP,ENT,A QA,B QB,C QC,D QD,RCO,163,CLK,CLR,LD,ENP,ENT,A QA,B QB,C QC,D QD,RCO,163,SYNC,+5,V,CLK,EN,1D 1Q,2D 2Q,3D 3Q,4D 4Q,5D 5Q,6D 6Q,7D 7Q,8D 8Q,74,x377,并行,数据,位数,+5,V,+5,V,串,/,并转换,RD,PD,BIT0_L,串,/,并转换,第三次作业,8.16*,8.55,8.58,(,参考表,8-25),