第七讲 组合逻辑电路的Verilog设计.ppt

Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,组合逻辑电路的,Verilog,设计,复习,组合逻辑电路的概念,组合逻辑电路的特点,组合逻辑的描述方法,常用的组合逻辑电路,描述设计的三种基本方式,数据流方式,assign,语句,结构方式,模块、原语实例化,行为方式,always,、,initial,语句,Verilog,描述组合逻辑电路,assign,语句（被赋值类型？）,always,语句（敏感事件？赋值类型？）,门原语,基本门电路的,Verilog,描述,1.assign,语句,assign out=a,2.,门原语,xor,xor1(out,a,b);,三态门的,Verilog,描述,1.assign,语句,assign,dout,=en?din:,bz,;,2.,条件语句,if(en=1),dout,=din;,else,dout,=,bz,;,全加器的,Verilog,描述,wire 3:0,x,y,;wire,cin,;,reg,3:0 sum;,reg,cout,;,描述,1,：,assign,cout,sum=x+y+,cin,;,描述,2,：,always (x or y orcin,),begin,cout,sum,=x+y+,cin,;,end,描述,3,：。,FPGA,器件中，通过快速进位通道可以提高加法器的运行速度,比较器的,Verilog,描述,if,语句,always (a or b),begin,if(a=b),agb,asb,aeb,=3b001;,else if(ab),agb,asb,aeb,=3b100;,else if(ab),agb,asb,aeb,=3b010;,else ,agb,asb,aeb,=3bxxx;,end,2.case,语句,编码器的,Verilog,描述,always (din),begin,case(din,),8b0000_0001:,dout,=3b000;,8b0000_0010:,dout,=3b001;,8b0000_0100:,dout,=3b010;,8b0000_1000:,dout,=3b011;,8b1000_0000:,dout,=3b111;,default:,dout,=3bx;,endcase,end,优先编码器的,Verilog,描述,always (din),begin,casex(din,),8b1xxx_xxxx:,dout,=3b111;,8b01xx_xxxx:,dout,=3b110;,8b001x_xxxx:,dout,=3b101;,8b0001_xxxx:,dout,=3b100;,8b0000_0001:,dout,=3b000;,default:,dout,=3bx;,endcase,end,多路选择器,always,begin,case(,sel,),2b00:Out=A;,2b01:Out=B;,2b10:Out=C;,2b11:Out=D;,default:Out=0;,endcase,end,应用实例,CPU,简单运算单元,MIPS,五级流水线结构,in1,in2,op,out,a,b,0001,a,a,b,0010,a+1,a,b,0011,a-1,a,b,0100,a+b,a,b,0101,a-b,a,b,0110,a&b,a,b0111,a|b,a,b,1000,ab,a,b,1001,a,a,b,1010,a1,运算单元功能表,具体电路结构,？,？,实现代码（,1,）,module,alu,(in1,in2,op,out);,input 15:0 in1,in2;,input 3:0 op;,output 15:0 out;,wire 15:0 in1,in2;,wire 3:0 op;,reg,15:0 out;,实现代码（,2,）,parameter Transfer =4b0001,Increase =4b0010,Decrease =4b0011,Addition =4b0100,Subtraction=4b0101,AND=4b0110,OR=4b0111,XOR=4b1000,NOT=4b1001,Shift_Left,=4b1010,Shift_Right,=4b1011;,parameter,与,define,的区别,always (in1 or in2 or op),begin,case(op),Transfer:out=in1;,Increase:out=in1+1;,Decrease:out=in1 1;,Addition:out=in1+in2;,Subtraction:out=in1 in2;,AND:out=a,OR :out=a|b;,XOR:out=a b;,NOT,：,out=a;,Shift_Left,:out=a 1;,endcase,end,谢谢,