电路设计专题.pptx

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,2015/1/11,#,电路设计专题,Design Entry,Schematic capture,Hardware Description Languages,Logic Synthesis,Pre layout verification,Functional simulation,Formal methods,Timing Analysis,Floorplanning,Placement,Routing,Extraction,Post layout verification,Logic,Design,Physical,Design,Typical Design Flow,形式验证是一个系统性的过程，将使用数学推理来验证设计意图（指标）在实现,(RTL),中是否得以贯彻。形式验证可以克服所有,3,种仿真挑战，由于形式验证能够从算法上穷尽检查所有随时间可能变化的输进值。,套用特定的时序模型，针对特定电路分析其是否违反设计者给定的时序限制。,CLBs Composed,of:,LUTs,(lookup tables):perform combinational logic,Flip-flops,:perform sequential functions,Multiplexers,:connect LUTs and,flip-flops,实际,FPGA,中实现逻辑的方式,Field programmable gate arrays(FPGAs),Array of configurable logic blocks(CLBs),LUT as key component,Perform combinational and sequential logic,Configuration is based on SRAM,Composed of:,CLBs,(Configurable logic blocks):perform logic,IOBs,(Input/output buffers):interface with outside world,Programmable interconnection,:connect CLBs and IOBs,Some FPGAs include other building blocks such as multipliers and RAMs,目录,组合逻辑,时序逻辑,同步时序逻辑,储存逻辑（包括,rom,逻辑）,优化方式（流水线、并行、,retiming,）,组合逻辑,Single-input:,NOT gate,buffer,Two-input:,AND,OR,XOR,NAND,NOR,XNOR,Multiple-input,选择器,2:1 Mux,这就是,lookup table,Appropriate data input,address,这个元件叫,multiplexer,Bool,代数,Truth table,lookup table,K map,LUT,电路,lookuptable,技巧,技巧,Reducing the size of the Mux,Reduce the width of address,Flow:,Move some lines to input,The remaining lines in the address are looped overall,Generate the appropriate logic using the moved lines,Verilog,module example(input,wire,a,b,c,output,wire,y);,assign y=a,Endmodule,module mux2(input,logic,3:0 d0,d1,input logic s,output logic 3:0 y);,assign y=s?d1:d0;,endmodule,Verilog,NOT,*,/,%,mult,div,mod,+,-,add,sub,shift,arithmetic shift,=,comparison,=,!=,equal,not equal,&,&,AND,NAND,XOR,XNOR,|,|,OR,NOR,?:,ternary operator,Number,#Bits,Base,Decimal Equivalent,Stored,3,b101,3,binary,5,101,b11,unsized,binary,3,000011,8,b11,8,binary,3,00000011,8,b1010_1011,8,binary,171,10101011,3,d6,3,decimal,6,110,6,o42,6,octal,34,100010,8,hAB,8,hexadecimal,171,10101011,42,Unsized,decimal,42,000101010,Verilog,/combinational logic using an always statement,module gates(input 3:0 a,b,output reg 3:0 y1,y2,y3,y4,y5);,always(*)/need begin/end because there is,begin /more than one statement in always,y1=a /AND,y2=a|b;/OR,y3=a b;/XOR,y4=(a /NAND,y5=(a|b);/NOR,end,endmodule,Verilogmodule sevenseg(input 3:0 data,output reg 6:0 segments);,always(*),case(data),/abc_defg,0:segments=7b111_1110;,1:segments=7b011_0000;,2:segments=7b110_1101;,3:segments=7b111_1001;,4:segments=7b011_0011;,5:segments=7b101_1011;,6:segments=7b101_1111;,7:segments=7b111_0000;,8:segments=7b111_1111;,9:segments=7b111_1011;,default:segments=7b000_0000;,/required,or produces/latch,endcase,endmodule,时序逻辑,1.Bistable,Circuit,2.SR,(Set/Reset)Latch,3.D,Latch Internal Circuit,时序逻辑元件最终进化版,4,.D Flip-Flop,Registers,Verilog,代码：,可以看做在触发器处保存了一个值，在每次上升延时修改它。同时，这个值就是触发器输出。,Verilog,module flop(input clk,input 3:0 d,output,reg,3:0 q);,always (posedge clk),q=d;/pronounced“q gets d”,endmodule,Verilog,module flopr(input clk,input reset,input 3:0 d,output reg 3:0 q);,/synchronous reset,always (posedge clk),if(reset)q=4b0;,else q=d;,endmodule,Verilog,module flopr(input clk,input reset,input 3:0 d,output reg 3:0 q);,/asynchronous reset,always (posedge clk,posedge reset),if(reset)q=4b0;,else q=d;,endmodule,Verilog,module flopren(input clk,input reset,input en,input 3:0 d,output reg 3:0 q);,/asynchronous reset and enable,always (posedge clk,posedge reset)/not good,if (reset)q=4b0;,else if(en)q=d;/what happens if en=0?,endmodule,Verilog,module latch(input clk,input 3:0 d,output reg 3:0 q);,always (clk,d),if(clk)q=d;,endmodule,Warning:,We wont use latches in this course,but you might write code that inadvertently implies a latch.So if your synthesized hardware has latches in it,this indicates an error.,Every cyclic path contains at least one register.why,？,在回路中没有状态机会导致在其中一些输入中输出或中间变量的值迅速发生改变，这导致了系统无法维持某一恒定状态。,Synchronous sequential logic,使用触发器记录系统状态，并且系统的状态会影响输出；,同时系统的状态会维持一定时间，这段时间内输入无法影响输出。,实现了：,FSM,记忆系统,流水线,触发器充当闸门优化设计,组合逻辑实现功能逻辑，时序逻辑构建架构。,Synchronous sequential logic,FSM,Moore,交通灯,Current State,Inputs,Next State,S,1,S,0,T,A,T,B,S,1,S,0,0,0,0,X,0,1,0,0,1,X,0,0,0,1,X,X,1,0,1,0,X,0,1,1,1,0,X,1,1,0,1,1,X,X,0,0,Current State,Outputs,S,1,S,0,L,A,1,L,A,0,L,B,1,L,B,0,0,0,0,0,1,0,0,1,0,1,1,0,1,0,1,0,0,0,1,1,1,0,0,1,S,1,=S,1,S,0,S,0,=S,1,S,0,T,A,+S,1,S,0,T,B,L,A,1,=S,1,L,A,0,=S,1,S,0,L,B,1,=S,1,L,B,0,=S1,S,0,输出比状态的转变迟一个周期,不使用,flip-flop,会怎样？,触发器记录系统当前的状态，使用有限状态机的意义在于使每个状态持续特定的时间，然后在上升沿触发。如果不使用触发器会导致设计不符合要求。,Pattern Recognizer Moore FSM,module patternMoore(input clk,input reset,input a,output y);,reg 2:0 state,nextstate;,parameter S0=3b000;,/state encoding,parameter S1=3b001;,parameter S2=3b010;,parameter S3=3b011;,parameter S4=3b100;,/State Register,always(posedge clk,posedge reset),if(reset)state=S0;,else state=nextstate;,/Next State Logic,always(*),case(state),S0:if(a)nextstate=S1;,else nextstate=S0;,S1:if(a)nextstate=S2;,else nextstate=S0;,S2:if(a)nextstate=S2;,else nextstate=S3;,S3:if(a)nextstate=S4;,else nextstate=S0;,S4:if(a)nextstate=S2;,else nextstate=S0;,default:,nextstate=S0;,endcase,/Output Logic,assign y=(state=S4);,endmodule,Pattern Recognizer Moore FSM,module patternMoore(input clk,input reset,input a,output y);,reg 2:0,state;,parameter S0=3b000;,/state encoding,parameter S1=3b001;,parameter S2=3b010;,parameter S3=3b011;,parameter S4=3b100;,/Next State Logic,always(posedge clk,posedge reset),if(reset)state=S0;,else,case(state),S0:if(a),state=,S1;,else,state,=S0;,S1:if(a),state=,S2;,else,state=,S0;,S2:if(a),state=,S2;,else,state=,S3;,S3:if(a),state,=S4;,else,state=,S0;,S4:if(a),state,=S2;,else,state=,S0;,default:,state=,S0;,endcase,/Output Logic,assign y=(state=S4);,endmodule,同时包含了触发器和状态转换逻辑（组合逻辑）,不同的代码风格，但能得到同样的仿真结果（？）,为什么要做电路图分析？,Verilog,是面向硬件的变成，使用,verilog,描述电路：,1,必须可综合；,2,不同的代码风格得到不同的电路。心中有电路，才能写出好的,verilog,代码。,虽然,verilog,代码在,fpga,板上使用的是可编程门阵列电路实现，不一定是按照综合出的电路（测试过程），但是综合出的电路才能生产,asic,（专用集成电路）,工程中第二种实现方式对应的电路图是什么？,同样，两个组合逻辑电路，一个,D,触发器,为什么第一种方法会导致输出延期？,理论上两种代码都会,这是,moore,状态机的结构决定的,蜗牛在,1101,时微笑,Current State,Input,Next State,Output,S,1,S,0,A,S,1,S,0,Y,0,0,0,0,0,0,0,0,1,0,1,0,0,1,0,0,0,0,0,1,1,1,0,0,1,0,0,1,1,0,1,0,1,1,0,0,1,1,0,0,0,0,1,1,1,0,1,1,Mealy,Pattern Recognizer Mealy FSM,module patternMealy(input clk,input reset,input a,output y);,reg 1:0 state,nextstate;,parameter S0=2b00;,/state encoding,parameter S1=2b01;,parameter S2=2b10;,parameter S3=2b11;,/State Register,always(posedge clk,posedge reset),if(reset)state=S0;,else state=nextstate;,/Next State Logic,always(*),case(state),S0:if(a)nextstate=S1;,else nextstate=S0;,S1:if(a)nextstate=S2;,else nextstate=S0;,S2:if(a)nextstate=S2;,else nextstate=S3;,S3:if(a)nextstate=S1;,else nextstate=S0;,default,:nextstate=S0;,endcase,/Output Logic,assign y=(,a&,state=S3);,endmodule,Synchronous logic,Pipelining(,优化）,ROM logic,X,=,AB,Y,=,A,+,B,Z,=,A B,Memory logic,Data,2,=,A,1,A,0,Data,1,=,A,1,+,A,0,Data,0,=,A,1,A,0,40,/256 x 3 memory module with one read/write port,module dmem(input clk,we,input 7:0 a,input 2:0 wd,output 2:0 rd);,reg 2:0RAM255:0;,assign rd=RAMa;,always(posedge clk),if(we),RAMa=wd;,endmodule,Verilog Memory Arrays,补充,优化,Parallelizing,Throughput,注意事项,Duplicated area!,Duplicated I/O bandwidth!,Duplicated static power and dynamic power!,Notes for Parallelizing,Exploit temporal parallelism first(pipelining),Then spatial parallelism:parallelizing(can apply both),优化,retiming,