1、/*****
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****/
module myCPU(clk,reset_n,DataIn,DataOut);
parameter ADD=4'd10,MIN=4'd11,MUL=4'd12,DIV=4'd13,EQUAL=4'd14,Eorr=4'd15;
input clk,reset_n;
input [3:
2、0] DataIn; //Êý¾ÝÊäÈ룬0~9ΪÏàÓ¦ÊýÖµ£¬A~FΪ²Ù×÷Ö¸Áî
output [31:0] DataOut; //¹©ÏÔʾÓÃ
reg [31:0] DataOut;
reg [31:0] DataNew;
reg [31:0] DataOld;
reg enData; //Ñ¡Ôñ ÔËËã½á¹û »òÕß µ±Ç°ÊäÈë×öΪÏÔʾÊä³ö
always @(posedge clk)
begin
if(!reset_n)
3、 begin
DataOld = 32'd0;
DataOut = 32'd0;
DataNew = 16'd0;
end
else
begin
case(DataIn)
ADD:begin DataOld =DataOld+DataNew; enData=1'b0;end
4、 MIN:begin DataOld =DataOld-DataNew; enData=1'b0;end
MUL:begin DataOld =DataOld*DataNew; enData=1'b0;end
DIV:begin DataOld =DataOld/DataNew; enData=1'b0;end
EQUAL: enData=1
5、'b0; //Ö»ÊÇÏÔʾ½á¹û
Eorr: enData=1'bz; /*Êý¾ÝÎÞЧ*/
default
begin
DataNew =10*DataNew+DataIn;
enData=1'b1;
6、 end
endcase
if(enData)
begin
DataOut=DataNew;
end
else
begin DataOut=DataOld; DataNew = 16'd0; end
end
end
endmodule
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